diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2014-10-17 10:26:21 -0700 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-10-18 01:39:08 +0000 |
| commit | 18cc8ab5fdb9f564397b7d8a10234606964e3cee (patch) | |
| tree | 7305ff5e206b7577c7b291af1cc5772f3e502fc2 /board/samus | |
| parent | 1246bca1f87661d2f316471e16c9281fa4a036c8 (diff) | |
| download | chrome-ec-18cc8ab5fdb9f564397b7d8a10234606964e3cee.tar.gz | |
samus: Wait for VCORE_PGOOD before asserting SYS_PWROK
VCORE needs time to come up after PCH_PWROK is asserted and we
should be waiting for VCORE_PGOOD to be 1 before proceeding.
This also moves the 5ms delay for PCIe to be before SYS_PWROK
since that is where it is requried according to the power
sequence specification (rev 1.3 figure 2-4).
BUG=chrome-os-partner:33027
BRANCH=samus
TEST=build and boot on samus
Change-Id: I4bd969bdb56ecf14cc68754318452861b70f0539
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/224033
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Diffstat (limited to 'board/samus')
| -rw-r--r-- | board/samus/power_sequence.c | 33 |
1 files changed, 25 insertions, 8 deletions
diff --git a/board/samus/power_sequence.c b/board/samus/power_sequence.c index 0185a40fd8..3e42d3aebd 100644 --- a/board/samus/power_sequence.c +++ b/board/samus/power_sequence.c @@ -363,8 +363,10 @@ enum power_state power_handle_state(enum power_state state) /* Wait for non-core power rails good */ if (power_wait_signals(IN_PGOOD_S0)) { - chipset_force_shutdown(); + gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 0); wireless_set_state(WIRELESS_OFF); + gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 1); + chipset_force_shutdown(); return POWER_S3; } @@ -378,13 +380,6 @@ enum power_state power_handle_state(enum power_state state) disable_sleep(SLEEP_MASK_AP_RUN); /* - * Wait a bit for all voltages to be good. PCIe devices need - * 99ms, but mini-PCIe devices only need 1ms. Intel recommends - * at least 5ms between ALL_SYS_PWRGD and SYS_PWROK. - */ - msleep(5); - - /* * Throttle CPU if necessary. This should only be asserted * when +VCCP is powered (it is by now). */ @@ -392,6 +387,28 @@ enum power_state power_handle_state(enum power_state state) /* Set PCH_PWROK */ gpio_set_level(GPIO_PCH_PWROK, 1); + + /* Wait for VCORE_PGOOD before enabling SYS_PWROK */ + if (power_wait_signals(IN_PGOOD_VCORE)) { + hook_notify(HOOK_CHIPSET_SUSPEND); + enable_sleep(SLEEP_MASK_AP_RUN); + gpio_set_level(GPIO_PCH_PWROK, 0); + gpio_set_level(GPIO_CPU_PROCHOT, 0); + gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 0); + gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 1); + wireless_set_state(WIRELESS_OFF); + chipset_force_shutdown(); + return POWER_S3; + } + + /* + * Wait a bit for all voltages to be good. PCIe devices need + * 99ms, but mini-PCIe devices only need 1ms. Intel recommends + * at least 5ms between ALL_SYS_PWRGD and SYS_PWROK. + */ + msleep(5); + + /* Set SYS_PWROK */ gpio_set_level(GPIO_SYS_PWROK, 1); return POWER_S0; |