diff options
| author | Gwendal Grignou <gwendal@chromium.org> | 2019-03-11 15:57:52 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-03-26 04:42:55 -0700 |
| commit | bb266fc26fc05d4ab22de6ad7bce5b477c9f9140 (patch) | |
| tree | f6ada087f62246c3a9547e649ac8846b0ed6d5ab /board/samus_pd | |
| parent | 0bfc511527cf2aebfa163c63a1d028419ca0b0c3 (diff) | |
| download | chrome-ec-bb266fc26fc05d4ab22de6ad7bce5b477c9f9140.tar.gz | |
common: replace 1 << digits, with BIT(digits)
Requested for linux integration, use BIT instead of 1 <<
First step replace bit operation with operand containing only digits.
Fix an error in motion_lid try to set bit 31 of a signed integer.
BUG=None
BRANCH=None
TEST=compile
Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518659
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'board/samus_pd')
| -rw-r--r-- | board/samus_pd/board.c | 4 | ||||
| -rw-r--r-- | board/samus_pd/usb_pd_config.h | 10 |
2 files changed, 7 insertions, 7 deletions
diff --git a/board/samus_pd/board.c b/board/samus_pd/board.c index 3087b9ce03..7691865476 100644 --- a/board/samus_pd/board.c +++ b/board/samus_pd/board.c @@ -181,7 +181,7 @@ void pch_evt(enum gpio_signal signal) void board_config_pre_init(void) { /* enable SYSCFG clock */ - STM32_RCC_APB2ENR |= 1 << 0; + STM32_RCC_APB2ENR |= BIT(0); /* * the DMA mapping is : * Chan 2 : TIM1_CH1 (C0 RX) @@ -196,7 +196,7 @@ void board_config_pre_init(void) * Remap USART1 RX/TX DMA to match uart driver. Remap SPI2 RX/TX and * TIM3_CH1 for unique DMA channels. */ - STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10) | (1 << 24) | (1 << 30); + STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10) | BIT(24) | BIT(30); } #include "gpio_list.h" diff --git a/board/samus_pd/usb_pd_config.h b/board/samus_pd/usb_pd_config.h index d303ae3a51..0f152a7362 100644 --- a/board/samus_pd/usb_pd_config.h +++ b/board/samus_pd/usb_pd_config.h @@ -64,7 +64,7 @@ static inline void spi_enable_clock(int port) #define TIM_TX_CCR_IDX(p) ((p) ? TIM_TX_CCR_C1 : TIM_TX_CCR_C0) #define TIM_RX_CCR_IDX(p) ((p) ? TIM_RX_CCR_C1 : TIM_RX_CCR_C0) #define TIM_CCR_CS 1 -#define EXTI_COMP_MASK(p) ((p) ? (1<<22) : (1 << 21)) +#define EXTI_COMP_MASK(p) ((p) ? BIT(22) : BIT(21)) #define IRQ_COMP STM32_IRQ_COMP /* triggers packet detection on comparator falling edge */ #define EXTI_XTSR STM32_EXTI_FTSR @@ -93,12 +93,12 @@ static inline void pd_tx_spi_reset(int port) { if (port == 0) { /* Reset SPI2 */ - STM32_RCC_APB1RSTR |= (1 << 14); - STM32_RCC_APB1RSTR &= ~(1 << 14); + STM32_RCC_APB1RSTR |= BIT(14); + STM32_RCC_APB1RSTR &= ~BIT(14); } else { /* Reset SPI1 */ - STM32_RCC_APB2RSTR |= (1 << 12); - STM32_RCC_APB2RSTR &= ~(1 << 12); + STM32_RCC_APB2RSTR |= BIT(12); + STM32_RCC_APB2RSTR &= ~BIT(12); } } |