Merge remote-tracking branch cros/main into firmware-fpmcu-dartmonkey-releasefirmware-fpmcu-dartmonkey-release

Generated by: ./util/update_release_branch.py --board dartmonkey --relevant_paths_file
./util/fingerprint-relevant-paths.txt firmware-fpmcu-dartmonkey-release

Relevant changes:

git log --oneline 6c1587ca70..28712dae9d -- board/nocturne_fp
board/dartmonkey common/fpsensor docs/fingerprint driver/fingerprint
util/getversion.sh

ded9307b79 util/getversion.sh: Fix version when not in a git repo
956055e692 board: change Google USB vendor info
71b2ef709d Update license boilerplate text in source code files
33e11afda0 Revert "fpsensor: Build fpsensor source file with C++"
c8d0360723 fpsensor: Build fpsensor source file with C++
bc113abd53 fpsensor: Fix g++ compiler error
150a58a0dc fpsensor: Fix fp_set_sensor_mode return type
b33b5ce85b fpsensor: Remove nested designators for C++ compatibility
2e864b2539 tree-wide: const-ify argv for console commands
56d8b360f9 test: Add test for get ikm failure when seed not set
3a3d6c3690 test: Add test for fpsensor trivial key failure
233e6bbd08 fpsensor_crypto: Abstract calls to hmac_SHA256
0a041b285b docs/fingerprint: Typo correction
c03fab67e2 docs/fingerprint: Fix the path of fputils.py
0b5d4baf5a util/getversion.sh: Fix empty file list handling
6e128fe760 FPMCU dev board environment with Satlab
3eb29b6aa5 builtin: Move ssize_t to sys/types.h
345d62ebd1 docs/fingerprint: Update power numbers for latest dartmonkey release
c25ffdb316 common: Conditionally support printf %l and %i modifiers
9a3c514b45 test: Add a test to check if the debugger is connected
54e603413f Move standard library tests to their own file
43fa6b4bf8 docs/fingerprint: Update power numbers for latest bloonchipper release
25536f9a84 driver/fingerprint/fpc/bep/fpc_sensor_spi.c: Format with clang-format
4face99efd driver/fingerprint/fpc/libfp/fpc_sensor_pal.h: Format with clang-format
738de2b575 trng: Rename rand to trng_rand
14b8270edd docs/fingerprint: Update dragonclaw power numbers
0b268f93d1 driver/fingerprint/fpc/libfp/fpc_private.c: Format with clang-format
f80da163f2 driver/fingerprint/fpc/libfp/fpc_private.h: Format with clang-format
a0751778f4 board/nocturne_fp/ro_workarounds.c: Format with clang-format
5e9c85c9b1 driver/fingerprint/fpc/libfp/fpc_sensor_pal.c: Format with clang-format
c1f9dd3cf8 driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h: Format with clang-format
eb1e1bed8d driver/fingerprint/fpc/libfp/fpc1145_private.h: Format with clang-format
6e7b611821 driver/fingerprint/fpc/bep/fpc_bio_algorithm.h: Format with clang-format
e0589cd5e2 driver/fingerprint/fpc/bep/fpc1035_private.h: Format with clang-format
58f0246dbe board/nocturne_fp/board_ro.c: Format with clang-format
7905e556a0 common/fpsensor/fpsensor_crypto.c: Format with clang-format
21289d170c driver/fingerprint/fpc/bep/fpc1025_private.h: Format with clang-format
98a20f937e common/fpsensor/fpsensor_state.c: Format with clang-format
a2d255d8af common/fpsensor/fpsensor.c: Format with clang-format
84e53a65da board/nocturne_fp/board.h: Format with clang-format
73055eeb3f driver/fingerprint/fpc/bep/fpc_private.c: Format with clang-format
0f7b5cb509 common/fpsensor/fpsensor_private.h: Format with clang-format
1ceade6e65 driver/fingerprint/fpc/bep/fpc_private.h: Format with clang-format
dca9d74321 Revert "trng: Rename rand to trng_rand"
a6b0b3554f trng: Rename rand to trng_rand
28d0b75b70 third_party/boringssl: Remove unused header

BRANCH=None
BUG=b:244387210 b:242720240 b:215613183 b:242720910 b:236386294
BUG=b:234181908 b:244781166 b:234781655 b:234143158 b:234181908
BUG=b:237344361 b:236025198 b:234181908 b:180945056 chromium:1098010
BUG=b:246424843 b:234181908 b:131913998
TEST=`make -j buildall`
TEST=./util/run_device_tests.py --board dartmonkey
     Test "aes": PASSED
     Test "cec": PASSED
     Test "cortexm_fpu": PASSED
     Test "crc": PASSED
     Test "flash_physical": PASSED
     Test "flash_write_protect": PASSED
     Test "fpsensor_hw": PASSED
     Test "fpsensor_spi_ro": PASSED
     Test "fpsensor_spi_rw": PASSED
     Test "fpsensor_uart_ro": PASSED
     Test "fpsensor_uart_rw": PASSED
     Test "mpu_ro": PASSED
     Test "mpu_rw": PASSED
     Test "mutex": PASSED
     Test "pingpong": PASSED
     Test "printf": PASSED
     Test "queue": PASSED
     Test "rollback_region0": PASSED
     Test "rollback_region1": PASSED
     Test "rollback_entropy": PASSED
     Test "rtc": PASSED
     Test "sha256": PASSED
     Test "sha256_unrolled": PASSED
     Test "static_if": PASSED
     Test "stdlib": PASSED
     Test "system_is_locked_wp_on": PASSED
     Test "system_is_locked_wp_off": PASSED
     Test "timer_dos": PASSED
     Test "utils": PASSED
     Test "utils_str": PASSED
     Test "panic_data_dartmonkey_v2.0.2887": PASSED
     Test "panic_data_nocturne_fp_v2.2.64": PASSED
     Test "panic_data_nami_fp_v2.2.144": PASSED
Force-Relevant-Builds: all
Signed-off-by: Tom Hughes <tomhughes@chromium.org>

Change-Id: I2c312583a709fedae8fe11d92c22328c3b634bc7

1 files changed, 160 insertions, 160 deletions

diff --git a/board/servo_v4p1/fusb302b.h b/board/servo_v4p1/fusb302b.h
index ec89c0c207..cebf5409f5 100644
--- a/board/servo_v4p1/fusb302b.h
+++ b/board/servo_v4p1/fusb302b.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,173 +22,173 @@
 /* FUSB302B11MPX */
 #define FUSB302_I2C_ADDR_B11_FLAGS 0x25
 
-#define TCPC_REG_DEVICE_ID	0x01
-
-#define TCPC_REG_SWITCHES0	0x02
-#define TCPC_REG_SWITCHES0_CC2_PU_EN	(1<<7)
-#define TCPC_REG_SWITCHES0_CC1_PU_EN	(1<<6)
-#define TCPC_REG_SWITCHES0_VCONN_CC2	(1<<5)
-#define TCPC_REG_SWITCHES0_VCONN_CC1	(1<<4)
-#define TCPC_REG_SWITCHES0_MEAS_CC2	(1<<3)
-#define TCPC_REG_SWITCHES0_MEAS_CC1	(1<<2)
-#define TCPC_REG_SWITCHES0_CC2_PD_EN	(1<<1)
-#define TCPC_REG_SWITCHES0_CC1_PD_EN	(1<<0)
-
-#define TCPC_REG_SWITCHES1	0x03
-#define TCPC_REG_SWITCHES1_POWERROLE	(1<<7)
-#define TCPC_REG_SWITCHES1_SPECREV1	(1<<6)
-#define TCPC_REG_SWITCHES1_SPECREV0	(1<<5)
-#define TCPC_REG_SWITCHES1_DATAROLE	(1<<4)
-#define TCPC_REG_SWITCHES1_AUTO_GCRC	(1<<2)
-#define TCPC_REG_SWITCHES1_TXCC2_EN	(1<<1)
-#define TCPC_REG_SWITCHES1_TXCC1_EN	(1<<0)
-
-#define TCPC_REG_MEASURE	0x04
-#define TCPC_REG_MEASURE_MDAC_MASK	0x3F
-#define TCPC_REG_MEASURE_VBUS		(1<<6)
+#define TCPC_REG_DEVICE_ID 0x01
+
+#define TCPC_REG_SWITCHES0 0x02
+#define TCPC_REG_SWITCHES0_CC2_PU_EN (1 << 7)
+#define TCPC_REG_SWITCHES0_CC1_PU_EN (1 << 6)
+#define TCPC_REG_SWITCHES0_VCONN_CC2 (1 << 5)
+#define TCPC_REG_SWITCHES0_VCONN_CC1 (1 << 4)
+#define TCPC_REG_SWITCHES0_MEAS_CC2 (1 << 3)
+#define TCPC_REG_SWITCHES0_MEAS_CC1 (1 << 2)
+#define TCPC_REG_SWITCHES0_CC2_PD_EN (1 << 1)
+#define TCPC_REG_SWITCHES0_CC1_PD_EN (1 << 0)
+
+#define TCPC_REG_SWITCHES1 0x03
+#define TCPC_REG_SWITCHES1_POWERROLE (1 << 7)
+#define TCPC_REG_SWITCHES1_SPECREV1 (1 << 6)
+#define TCPC_REG_SWITCHES1_SPECREV0 (1 << 5)
+#define TCPC_REG_SWITCHES1_DATAROLE (1 << 4)
+#define TCPC_REG_SWITCHES1_AUTO_GCRC (1 << 2)
+#define TCPC_REG_SWITCHES1_TXCC2_EN (1 << 1)
+#define TCPC_REG_SWITCHES1_TXCC1_EN (1 << 0)
+
+#define TCPC_REG_MEASURE 0x04
+#define TCPC_REG_MEASURE_MDAC_MASK 0x3F
+#define TCPC_REG_MEASURE_VBUS (1 << 6)
 /*
  * MDAC reference voltage step size is 42 mV. Round our thresholds to reduce
  * maximum error, which also matches suggested thresholds in datasheet
  * (Table 3. Host Interrupt Summary).
  */
-#define TCPC_REG_MEASURE_MDAC_MV(mv)	(DIV_ROUND_NEAREST((mv), 42) & 0x3f)
-
-#define TCPC_REG_CONTROL0	0x06
-#define TCPC_REG_CONTROL0_TX_FLUSH	(1<<6)
-#define TCPC_REG_CONTROL0_INT_MASK	(1<<5)
-#define TCPC_REG_CONTROL0_HOST_CUR_MASK (3<<2)
-#define TCPC_REG_CONTROL0_HOST_CUR_3A0  (3<<2)
-#define TCPC_REG_CONTROL0_HOST_CUR_1A5  (2<<2)
-#define TCPC_REG_CONTROL0_HOST_CUR_USB  (1<<2)
-#define TCPC_REG_CONTROL0_TX_START	(1<<0)
-
-#define TCPC_REG_CONTROL1	0x07
-#define TCPC_REG_CONTROL1_ENSOP2DB	(1<<6)
-#define TCPC_REG_CONTROL1_ENSOP1DB	(1<<5)
-#define TCPC_REG_CONTROL1_BIST_MODE2	(1<<4)
-#define TCPC_REG_CONTROL1_RX_FLUSH	(1<<2)
-#define TCPC_REG_CONTROL1_ENSOP2	(1<<1)
-#define TCPC_REG_CONTROL1_ENSOP1	(1<<0)
-
-#define TCPC_REG_CONTROL2	0x08
+#define TCPC_REG_MEASURE_MDAC_MV(mv) (DIV_ROUND_NEAREST((mv), 42) & 0x3f)
+
+#define TCPC_REG_CONTROL0 0x06
+#define TCPC_REG_CONTROL0_TX_FLUSH (1 << 6)
+#define TCPC_REG_CONTROL0_INT_MASK (1 << 5)
+#define TCPC_REG_CONTROL0_HOST_CUR_MASK (3 << 2)
+#define TCPC_REG_CONTROL0_HOST_CUR_3A0 (3 << 2)
+#define TCPC_REG_CONTROL0_HOST_CUR_1A5 (2 << 2)
+#define TCPC_REG_CONTROL0_HOST_CUR_USB (1 << 2)
+#define TCPC_REG_CONTROL0_TX_START (1 << 0)
+
+#define TCPC_REG_CONTROL1 0x07
+#define TCPC_REG_CONTROL1_ENSOP2DB (1 << 6)
+#define TCPC_REG_CONTROL1_ENSOP1DB (1 << 5)
+#define TCPC_REG_CONTROL1_BIST_MODE2 (1 << 4)
+#define TCPC_REG_CONTROL1_RX_FLUSH (1 << 2)
+#define TCPC_REG_CONTROL1_ENSOP2 (1 << 1)
+#define TCPC_REG_CONTROL1_ENSOP1 (1 << 0)
+
+#define TCPC_REG_CONTROL2 0x08
 /* two-bit field, valid values below */
-#define TCPC_REG_CONTROL2_MODE_MASK	(0x3<<TCPC_REG_CONTROL2_MODE_POS)
-#define TCPC_REG_CONTROL2_MODE_DFP	(0x3)
-#define TCPC_REG_CONTROL2_MODE_UFP	(0x2)
-#define TCPC_REG_CONTROL2_MODE_DRP	(0x1)
-#define TCPC_REG_CONTROL2_MODE_POS	(1)
-#define TCPC_REG_CONTROL2_TOGGLE	(1<<0)
-
-#define TCPC_REG_CONTROL3	0x09
-#define TCPC_REG_CONTROL3_SEND_HARDRESET	(1<<6)
-#define TCPC_REG_CONTROL3_BIST_TMODE		(1<<5) /* 302B Only */
-#define TCPC_REG_CONTROL3_AUTO_HARDRESET	(1<<4)
-#define TCPC_REG_CONTROL3_AUTO_SOFTRESET	(1<<3)
+#define TCPC_REG_CONTROL2_MODE_MASK (0x3 << TCPC_REG_CONTROL2_MODE_POS)
+#define TCPC_REG_CONTROL2_MODE_DFP (0x3)
+#define TCPC_REG_CONTROL2_MODE_UFP (0x2)
+#define TCPC_REG_CONTROL2_MODE_DRP (0x1)
+#define TCPC_REG_CONTROL2_MODE_POS (1)
+#define TCPC_REG_CONTROL2_TOGGLE (1 << 0)
+
+#define TCPC_REG_CONTROL3 0x09
+#define TCPC_REG_CONTROL3_SEND_HARDRESET (1 << 6)
+#define TCPC_REG_CONTROL3_BIST_TMODE (1 << 5) /* 302B Only */
+#define TCPC_REG_CONTROL3_AUTO_HARDRESET (1 << 4)
+#define TCPC_REG_CONTROL3_AUTO_SOFTRESET (1 << 3)
 /* two-bit field */
-#define TCPC_REG_CONTROL3_N_RETRIES		(1<<1)
-#define TCPC_REG_CONTROL3_N_RETRIES_POS		(1)
-#define TCPC_REG_CONTROL3_N_RETRIES_SIZE	(2)
-#define TCPC_REG_CONTROL3_AUTO_RETRY		(1<<0)
-
-#define TCPC_REG_MASK		0x0A
-#define TCPC_REG_MASK_VBUSOK		(1<<7)
-#define TCPC_REG_MASK_ACTIVITY		(1<<6)
-#define TCPC_REG_MASK_COMP_CHNG		(1<<5)
-#define TCPC_REG_MASK_CRC_CHK		(1<<4)
-#define TCPC_REG_MASK_ALERT		(1<<3)
-#define TCPC_REG_MASK_WAKE		(1<<2)
-#define TCPC_REG_MASK_COLLISION		(1<<1)
-#define TCPC_REG_MASK_BC_LVL		(1<<0)
-
-#define TCPC_REG_POWER		0x0B
-#define TCPC_REG_POWER_PWR		(1<<0)	/* four-bit field */
-#define TCPC_REG_POWER_PWR_LOW		0x1 /* Bandgap + Wake circuitry */
-#define TCPC_REG_POWER_PWR_MEDIUM	0x3 /* LOW + Receiver + Current refs */
-#define TCPC_REG_POWER_PWR_HIGH		0x7 /* MEDIUM + Measure block */
-#define TCPC_REG_POWER_PWR_ALL		0xF /* HIGH + Internal Oscillator */
-
-#define TCPC_REG_RESET		0x0C
-#define TCPC_REG_RESET_PD_RESET		(1<<1)
-#define TCPC_REG_RESET_SW_RESET		(1<<0)
-
-#define TCPC_REG_MASKA		0x0E
-#define TCPC_REG_MASKA_OCP_TEMP		(1<<7)
-#define TCPC_REG_MASKA_TOGDONE		(1<<6)
-#define TCPC_REG_MASKA_SOFTFAIL		(1<<5)
-#define TCPC_REG_MASKA_RETRYFAIL	(1<<4)
-#define TCPC_REG_MASKA_HARDSENT		(1<<3)
-#define TCPC_REG_MASKA_TX_SUCCESS	(1<<2)
-#define TCPC_REG_MASKA_SOFTRESET	(1<<1)
-#define TCPC_REG_MASKA_HARDRESET	(1<<0)
-
-#define TCPC_REG_MASKB		0x0F
-#define TCPC_REG_MASKB_GCRCSENT		(1<<0)
-
-#define TCPC_REG_STATUS0A	0x3C
-#define TCPC_REG_STATUS0A_SOFTFAIL	(1<<5)
-#define TCPC_REG_STATUS0A_RETRYFAIL	(1<<4)
-#define TCPC_REG_STATUS0A_POWER		(1<<2) /* two-bit field */
-#define TCPC_REG_STATUS0A_RX_SOFT_RESET	(1<<1)
-#define TCPC_REG_STATUS0A_RX_HARD_RESEt	(1<<0)
-
-#define TCPC_REG_STATUS1A	0x3D
+#define TCPC_REG_CONTROL3_N_RETRIES (1 << 1)
+#define TCPC_REG_CONTROL3_N_RETRIES_POS (1)
+#define TCPC_REG_CONTROL3_N_RETRIES_SIZE (2)
+#define TCPC_REG_CONTROL3_AUTO_RETRY (1 << 0)
+
+#define TCPC_REG_MASK 0x0A
+#define TCPC_REG_MASK_VBUSOK (1 << 7)
+#define TCPC_REG_MASK_ACTIVITY (1 << 6)
+#define TCPC_REG_MASK_COMP_CHNG (1 << 5)
+#define TCPC_REG_MASK_CRC_CHK (1 << 4)
+#define TCPC_REG_MASK_ALERT (1 << 3)
+#define TCPC_REG_MASK_WAKE (1 << 2)
+#define TCPC_REG_MASK_COLLISION (1 << 1)
+#define TCPC_REG_MASK_BC_LVL (1 << 0)
+
+#define TCPC_REG_POWER 0x0B
+#define TCPC_REG_POWER_PWR (1 << 0) /* four-bit field */
+#define TCPC_REG_POWER_PWR_LOW 0x1 /* Bandgap + Wake circuitry */
+#define TCPC_REG_POWER_PWR_MEDIUM 0x3 /* LOW + Receiver + Current refs */
+#define TCPC_REG_POWER_PWR_HIGH 0x7 /* MEDIUM + Measure block */
+#define TCPC_REG_POWER_PWR_ALL 0xF /* HIGH + Internal Oscillator */
+
+#define TCPC_REG_RESET 0x0C
+#define TCPC_REG_RESET_PD_RESET (1 << 1)
+#define TCPC_REG_RESET_SW_RESET (1 << 0)
+
+#define TCPC_REG_MASKA 0x0E
+#define TCPC_REG_MASKA_OCP_TEMP (1 << 7)
+#define TCPC_REG_MASKA_TOGDONE (1 << 6)
+#define TCPC_REG_MASKA_SOFTFAIL (1 << 5)
+#define TCPC_REG_MASKA_RETRYFAIL (1 << 4)
+#define TCPC_REG_MASKA_HARDSENT (1 << 3)
+#define TCPC_REG_MASKA_TX_SUCCESS (1 << 2)
+#define TCPC_REG_MASKA_SOFTRESET (1 << 1)
+#define TCPC_REG_MASKA_HARDRESET (1 << 0)
+
+#define TCPC_REG_MASKB 0x0F
+#define TCPC_REG_MASKB_GCRCSENT (1 << 0)
+
+#define TCPC_REG_STATUS0A 0x3C
+#define TCPC_REG_STATUS0A_SOFTFAIL (1 << 5)
+#define TCPC_REG_STATUS0A_RETRYFAIL (1 << 4)
+#define TCPC_REG_STATUS0A_POWER (1 << 2) /* two-bit field */
+#define TCPC_REG_STATUS0A_RX_SOFT_RESET (1 << 1)
+#define TCPC_REG_STATUS0A_RX_HARD_RESEt (1 << 0)
+
+#define TCPC_REG_STATUS1A 0x3D
 /* three-bit field, valid values below */
-#define TCPC_REG_STATUS1A_TOGSS		(1<<3)
-#define TCPC_REG_STATUS1A_TOGSS_RUNNING		0x0
-#define TCPC_REG_STATUS1A_TOGSS_SRC1		0x1
-#define TCPC_REG_STATUS1A_TOGSS_SRC2		0x2
-#define TCPC_REG_STATUS1A_TOGSS_SNK1		0x5
-#define TCPC_REG_STATUS1A_TOGSS_SNK2		0x6
-#define TCPC_REG_STATUS1A_TOGSS_AA		0x7
-#define TCPC_REG_STATUS1A_TOGSS_POS		(3)
-#define TCPC_REG_STATUS1A_TOGSS_MASK		(0x7)
-
-#define TCPC_REG_STATUS1A_RXSOP2DB	(1<<2)
-#define TCPC_REG_STATUS1A_RXSOP1DB	(1<<1)
-#define TCPC_REG_STATUS1A_RXSOP		(1<<0)
-
-#define TCPC_REG_INTERRUPTA	0x3E
-#define TCPC_REG_INTERRUPTA_OCP_TEMP	(1<<7)
-#define TCPC_REG_INTERRUPTA_TOGDONE	(1<<6)
-#define TCPC_REG_INTERRUPTA_SOFTFAIL	(1<<5)
-#define TCPC_REG_INTERRUPTA_RETRYFAIL	(1<<4)
-#define TCPC_REG_INTERRUPTA_HARDSENT	(1<<3)
-#define TCPC_REG_INTERRUPTA_TX_SUCCESS	(1<<2)
-#define TCPC_REG_INTERRUPTA_SOFTRESET	(1<<1)
-#define TCPC_REG_INTERRUPTA_HARDRESET	(1<<0)
-
-#define TCPC_REG_INTERRUPTB	0x3F
-#define TCPC_REG_INTERRUPTB_GCRCSENT		(1<<0)
-
-#define TCPC_REG_STATUS0	0x40
-#define TCPC_REG_STATUS0_VBUSOK		(1<<7)
-#define TCPC_REG_STATUS0_ACTIVITY	(1<<6)
-#define TCPC_REG_STATUS0_COMP		(1<<5)
-#define TCPC_REG_STATUS0_CRC_CHK	(1<<4)
-#define TCPC_REG_STATUS0_ALERT		(1<<3)
-#define TCPC_REG_STATUS0_WAKE		(1<<2)
-#define TCPC_REG_STATUS0_BC_LVL1	(1<<1) /* two-bit field */
-#define TCPC_REG_STATUS0_BC_LVL0	(1<<0) /* two-bit field */
-
-#define TCPC_REG_STATUS1	0x41
-#define TCPC_REG_STATUS1_RXSOP2		(1<<7)
-#define TCPC_REG_STATUS1_RXSOP1		(1<<6)
-#define TCPC_REG_STATUS1_RX_EMPTY	(1<<5)
-#define TCPC_REG_STATUS1_RX_FULL	(1<<4)
-#define TCPC_REG_STATUS1_TX_EMPTY	(1<<3)
-#define TCPC_REG_STATUS1_TX_FULL	(1<<2)
-
-#define TCPC_REG_INTERRUPT	0x42
-#define TCPC_REG_INTERRUPT_VBUSOK	(1<<7)
-#define TCPC_REG_INTERRUPT_ACTIVITY	(1<<6)
-#define TCPC_REG_INTERRUPT_COMP_CHNG	(1<<5)
-#define TCPC_REG_INTERRUPT_CRC_CHK	(1<<4)
-#define TCPC_REG_INTERRUPT_ALERT	(1<<3)
-#define TCPC_REG_INTERRUPT_WAKE		(1<<2)
-#define TCPC_REG_INTERRUPT_COLLISION	(1<<1)
-#define TCPC_REG_INTERRUPT_BC_LVL	(1<<0)
-
-#define TCPC_REG_FIFOS		0x43
+#define TCPC_REG_STATUS1A_TOGSS (1 << 3)
+#define TCPC_REG_STATUS1A_TOGSS_RUNNING 0x0
+#define TCPC_REG_STATUS1A_TOGSS_SRC1 0x1
+#define TCPC_REG_STATUS1A_TOGSS_SRC2 0x2
+#define TCPC_REG_STATUS1A_TOGSS_SNK1 0x5
+#define TCPC_REG_STATUS1A_TOGSS_SNK2 0x6
+#define TCPC_REG_STATUS1A_TOGSS_AA 0x7
+#define TCPC_REG_STATUS1A_TOGSS_POS (3)
+#define TCPC_REG_STATUS1A_TOGSS_MASK (0x7)
+
+#define TCPC_REG_STATUS1A_RXSOP2DB (1 << 2)
+#define TCPC_REG_STATUS1A_RXSOP1DB (1 << 1)
+#define TCPC_REG_STATUS1A_RXSOP (1 << 0)
+
+#define TCPC_REG_INTERRUPTA 0x3E
+#define TCPC_REG_INTERRUPTA_OCP_TEMP (1 << 7)
+#define TCPC_REG_INTERRUPTA_TOGDONE (1 << 6)
+#define TCPC_REG_INTERRUPTA_SOFTFAIL (1 << 5)
+#define TCPC_REG_INTERRUPTA_RETRYFAIL (1 << 4)
+#define TCPC_REG_INTERRUPTA_HARDSENT (1 << 3)
+#define TCPC_REG_INTERRUPTA_TX_SUCCESS (1 << 2)
+#define TCPC_REG_INTERRUPTA_SOFTRESET (1 << 1)
+#define TCPC_REG_INTERRUPTA_HARDRESET (1 << 0)
+
+#define TCPC_REG_INTERRUPTB 0x3F
+#define TCPC_REG_INTERRUPTB_GCRCSENT (1 << 0)
+
+#define TCPC_REG_STATUS0 0x40
+#define TCPC_REG_STATUS0_VBUSOK (1 << 7)
+#define TCPC_REG_STATUS0_ACTIVITY (1 << 6)
+#define TCPC_REG_STATUS0_COMP (1 << 5)
+#define TCPC_REG_STATUS0_CRC_CHK (1 << 4)
+#define TCPC_REG_STATUS0_ALERT (1 << 3)
+#define TCPC_REG_STATUS0_WAKE (1 << 2)
+#define TCPC_REG_STATUS0_BC_LVL1 (1 << 1) /* two-bit field */
+#define TCPC_REG_STATUS0_BC_LVL0 (1 << 0) /* two-bit field */
+
+#define TCPC_REG_STATUS1 0x41
+#define TCPC_REG_STATUS1_RXSOP2 (1 << 7)
+#define TCPC_REG_STATUS1_RXSOP1 (1 << 6)
+#define TCPC_REG_STATUS1_RX_EMPTY (1 << 5)
+#define TCPC_REG_STATUS1_RX_FULL (1 << 4)
+#define TCPC_REG_STATUS1_TX_EMPTY (1 << 3)
+#define TCPC_REG_STATUS1_TX_FULL (1 << 2)
+
+#define TCPC_REG_INTERRUPT 0x42
+#define TCPC_REG_INTERRUPT_VBUSOK (1 << 7)
+#define TCPC_REG_INTERRUPT_ACTIVITY (1 << 6)
+#define TCPC_REG_INTERRUPT_COMP_CHNG (1 << 5)
+#define TCPC_REG_INTERRUPT_CRC_CHK (1 << 4)
+#define TCPC_REG_INTERRUPT_ALERT (1 << 3)
+#define TCPC_REG_INTERRUPT_WAKE (1 << 2)
+#define TCPC_REG_INTERRUPT_COLLISION (1 << 1)
+#define TCPC_REG_INTERRUPT_BC_LVL (1 << 0)
+
+#define TCPC_REG_FIFOS 0x43
 
 /* Tokens defined for the FUSB302 TX FIFO */
 enum fusb302_txfifo_tokens {