diff options
author | Scott Worley <scott.worley@microchip.corp-partner.google.com> | 2021-02-03 10:31:16 -0500 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2021-02-10 06:22:01 +0000 |
commit | ccf7e98b4176c80780a80f53b465d992e09ce68d (patch) | |
tree | bf95ebda35a471ff47e674e52692d6882cfff3c8 /board/sklrvp_mchp | |
parent | 1ef386ef08ba298e937f92fb2df59659e0757879 (diff) | |
download | chrome-ec-ccf7e98b4176c80780a80f53b465d992e09ce68d.tar.gz |
mchp: Add MEC152x SKL RVP board
Add a MEC152x board based upon SKL-RVP using the intelrvp
baseboard. We use the fusb307 USB PD as a placeholder for
an actual USB PD. Added MCHP EC module to the intel RVP
baseboard.
BRANCH=none
BUG=b:177463787
TEST=Booted skylake RVP to Chrome OS
Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Change-Id: I4ea2e8ca27efa5b0624e751a06fcec8a1bf65456
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2673020
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Ravin Kumar <ravin.kumar@microchip.com>
Diffstat (limited to 'board/sklrvp_mchp')
l--------- | board/sklrvp_mchp/battery.c | 1 | ||||
-rw-r--r-- | board/sklrvp_mchp/board.c | 400 | ||||
-rw-r--r-- | board/sklrvp_mchp/board.h | 312 | ||||
-rw-r--r-- | board/sklrvp_mchp/build.mk | 19 | ||||
-rw-r--r-- | board/sklrvp_mchp/ec.tasklist | 25 | ||||
-rw-r--r-- | board/sklrvp_mchp/gpio.inc | 365 | ||||
-rw-r--r-- | board/sklrvp_mchp/lfw/gpio.inc | 41 |
7 files changed, 1163 insertions, 0 deletions
diff --git a/board/sklrvp_mchp/battery.c b/board/sklrvp_mchp/battery.c new file mode 120000 index 0000000000..569f81ec47 --- /dev/null +++ b/board/sklrvp_mchp/battery.c @@ -0,0 +1 @@ +../tglrvpu_ite/battery.c
\ No newline at end of file diff --git a/board/sklrvp_mchp/board.c b/board/sklrvp_mchp/board.c new file mode 100644 index 0000000000..c033c2bd7c --- /dev/null +++ b/board/sklrvp_mchp/board.c @@ -0,0 +1,400 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * Microchip Evaluation Board(EVB) with + * MEC1521H 144-pin processor card. + * EVB connected to Intel eSPI host chipset. + */ + +/* #include "bb_retimer.h" */ +#include "button.h" /* */ +#include "charger.h" /* */ +#include "chipset.h" +#include "driver/charger/isl9241.h" /* */ +#include "espi.h" +#include "extpower.h" +#include "driver/tcpm/fusb307.h" /* */ +#include "driver/tcpm/tcpci.h" +#include "gpio_chip.h" +#include "gpio.h" +#include "hooks.h" +#include "host_command.h" +#include "i2c.h" +#include "espi.h" +#include "lpc_chip.h" +#include "keyboard_scan.h" +#include "lid_switch.h" +#include "power.h" +#include "power/skylake.h" +#include "power_button.h" +#include "spi.h" +#include "spi_chip.h" +#include "switch.h" +#include "system.h" +#include "tablet_mode.h" +#include "task.h" +#include "timer.h" +#include "uart.h" +#include "usb_mux.h" /* */ +#include "usb_pd.h" +#include "usb_pd_tcpm.h" /* */ +#include "util.h" +#include "battery_smart.h" + +#include "gpio_list.h" + +#define CPUTS(outstr) cputs(CC_SYSTEM, outstr) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) + +/* + * NOTE: MCHP EVB + SKL RVP3 does not use BD99992 PMIC. + * RVP3 PMIC controlled by RVP3 logic. + */ +#define I2C_ADDR_BD99992_FLAGS 0x30 + +/* TCPC table of GPIO pins */ +const struct tcpc_gpio_config_t tcpc_gpios[] = { + [TYPE_C_PORT_0] = { + .vbus = { + .pin = GPIO_USB_C0_VBUS_INT, + .pin_pol = 1, + }, + .src = { + .pin = GPIO_USB_C0_SRC_EN, + .pin_pol = 1, + }, + .snk = { + .pin = GPIO_USB_C0_SNK_EN_L, + .pin_pol = 0, + }, + .src_ilim = { + .pin = GPIO_USB_C0_SRC_HI_ILIM, + .pin_pol = 1, + }, + }, + [TYPE_C_PORT_1] = { + .vbus = { + .pin = GPIO_USB_C1_VBUS_INT, + .pin_pol = 1, + }, + .src = { + .pin = GPIO_USB_C1_SRC_EN, + .pin_pol = 1, + }, + .snk = { + .pin = GPIO_USB_C1_SNK_EN_L, + .pin_pol = 0, + }, + .src_ilim = { + .pin = GPIO_USB_C1_SRC_HI_ILIM, + .pin_pol = 1, + }, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(tcpc_gpios) == CONFIG_USB_PD_PORT_MAX_COUNT); + +/* USB-C TPCP Configuration */ +const struct tcpc_config_t tcpc_config[] = { + [TYPE_C_PORT_0] = { + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = MCHP_I2C_PORT0, + .addr_flags = FUSB307_I2C_ADDR_FLAGS, + }, + .drv = &fusb307_tcpm_drv, + }, + [TYPE_C_PORT_1] = { + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = MCHP_I2C_PORT2, + .addr_flags = FUSB307_I2C_ADDR_FLAGS, + }, + .drv = &fusb307_tcpm_drv, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT); + +/* USB MUX Configuration */ +const struct usb_mux usb_muxes[] = { + [TYPE_C_PORT_0] = { + .usb_port = TYPE_C_PORT_0, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, + }, + [TYPE_C_PORT_1] = { + .usb_port = TYPE_C_PORT_1, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT); + +/* I2C ports */ +const struct i2c_port_t i2c_ports[] = { + /* + * Port-80 Display, Charger, Battery, IO-expanders, EEPROM, + * IMVP9, AUX-rail, power-monitor. + */ + [I2C_CHAN_BATT_CHG] = { + .name = "batt_chg", + .port = MCHP_I2C_PORT4, + .kbps = 100, + .scl = GPIO_SMB04_SCL, + .sda = GPIO_SMB04_SDA, + }, + /* other I2C devices */ + [I2C_CHAN_MISC] = { + .name = "misc", + .port = MCHP_I2C_PORT5, + .kbps = 100, + .scl = GPIO_SMB05_SCL, + .sda = GPIO_SMB05_SDA, + }, + [I2C_CHAN_TCPC_0] = { + .name = "tcpci0", + .port = MCHP_I2C_PORT0, + .kbps = 100, + .scl = GPIO_SMB00_SCL, + .sda = GPIO_SMB00_SDA, + }, + [I2C_CHAN_TCPC_1] = { + .name = "tcpci1", + .port = MCHP_I2C_PORT2, + .kbps = 100, + .scl = GPIO_SMB02_SCL, + .sda = GPIO_SMB02_SDA, + } +}; +BUILD_ASSERT(ARRAY_SIZE(i2c_ports) == I2C_CHAN_COUNT); +const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); + +/* Charger Chips */ +const struct charger_config_t chg_chips[] = { + { + .i2c_port = I2C_PORT_CHARGER, + .i2c_addr_flags = ISL9241_ADDR_FLAGS, + .drv = &isl9241_drv, + }, +}; + +/* + * MEC152x map ports to controller. + * Ports may map to the same controller. + */ +const uint16_t i2c_port_to_ctrl[I2C_PORT_COUNT] = { + (MCHP_I2C_CTRL0 << 8) + MCHP_I2C_PORT4, + (MCHP_I2C_CTRL1 << 8) + MCHP_I2C_PORT5, + (MCHP_I2C_CTRL2 << 8) + MCHP_I2C_PORT0, + (MCHP_I2C_CTRL3 << 8) + MCHP_I2C_PORT2, +}; + +/* + * Used by chip level I2C controller initialization. + * Board level can specify two unused I2C addresses + * for each controller. Current chip level disables + * controller response to address 0(general call). + */ +const uint32_t i2c_ctrl_slave_addrs[I2C_CONTROLLER_COUNT] = { + 0, 0, 0, 0 +}; + +/* + * default to I2C0 because callers may not check + * return value if we returned an error code. + */ +int board_i2c_p2c(int port) +{ + int i; + + for (i = 0; i < I2C_PORT_COUNT; i++) + if ((i2c_port_to_ctrl[i] & 0xFF) == port) + return (int)(i2c_port_to_ctrl[i] >> 8); + + return -1; +} + +/* Return the two slave addresses the specified + * controller will respond to when controller + * is acting as a slave. + * b[6:0] = b[7:1] of I2C address 1 + * b[14:8] = b[7:1] of I2C address 2 + * When not using I2C controllers as slaves we can use + * the same value for all controllers. The address should + * not be 0x00 as this is the general call address. + */ +uint16_t board_i2c_slave_addrs(int controller) +{ + int i; + + for (i = 0; i < I2C_CONTROLLER_COUNT; i++) + if ((i2c_ctrl_slave_addrs[i] & 0xffff) == controller) + return (i2c_ctrl_slave_addrs[i] >> 16); + + return CONFIG_MCHP_I2C0_SLAVE_ADDRS; +} + +static void sklrvp_init(void) +{ + int extpwr = extpower_is_present(); + + /* Provide AC status to the PCH */ + CPRINTS("Set PCH_ACOK = %d", extpwr); + gpio_set_level(GPIO_PCH_ACOK, extpwr); +} +DECLARE_HOOK(HOOK_INIT, sklrvp_init, HOOK_PRIO_DEFAULT); + +static void sklrvp_interrupt_init(void) +{ + /* Enable ALL_SYS_PWRGD interrupt */ + CPUTS("IEN ALL_SYS_PWRGD"); + gpio_enable_interrupt(GPIO_ALL_SYS_PWRGD); +} +DECLARE_HOOK(HOOK_INIT, sklrvp_interrupt_init, HOOK_PRIO_DEFAULT); + +/* Will this work for SKL-RVP */ +/******************************************************************************/ +/* PWROK signal configuration */ +/* + * SKL with MCHP EVB uses EC to handle ALL_SYS_PWRGD signal. + * MEC170x/MEC152x connected to SKL/KBL RVP3 reference board + * is required to monitor ALL_SYS_PWRGD and drive SYS_RESET_L + * after a 10 to 100 ms delay. + */ +#ifdef CONFIG_BOARD_EC_HANDLES_ALL_SYS_PWRGD + +static void board_all_sys_pwrgd(void) +{ + int allsys_in = gpio_get_level(GPIO_ALL_SYS_PWRGD); + int allsys_out = gpio_get_level(GPIO_SYS_RESET_L); + + if (allsys_in == allsys_out) + return; + + CPRINTS("ALL_SYS_PWRGD=%d SYS_RESET_L=%d", allsys_in, allsys_out); + + /* + * Wait at least 10 ms between power signals going high + */ + if (allsys_in) + msleep(100); + + if (!allsys_out) { + gpio_set_level(GPIO_SYS_RESET_L, allsys_in); + /* Force fan on for kabylake RVP */ + gpio_set_level(GPIO_EC_FAN1_PWM, 1); + CPRINTS("Set SYS_RESET_L = %d", allsys_in); + } +} +DECLARE_DEFERRED(board_all_sys_pwrgd); + +void board_all_sys_pwrgd_interrupt(enum gpio_signal signal) +{ + CPUTS("ISR ALL_SYS_PWRGD"); + hook_call_deferred(&board_all_sys_pwrgd_data, 0); +} +#endif /* #ifdef CONFIG_BOARD_HAS_ALL_SYS_PWRGD */ + +/* + * Returns board information (board id[7:0] and Fab id[15:8]) on success + * -1 on error. + */ +int board_get_version(void) +{ + int port0, port1; + int fab_id, board_id, bom_id; + + if (ioexpander_read_intelrvp_version(&port0, &port1)) + return -1; + /* + * Port0: bit 0 - BOM ID(2) + * bit 2:1 - FAB ID(1:0) + 1 + * Port1: bit 7:6 - BOM ID(1:0) + * bit 5:0 - BOARD ID(5:0) + */ + bom_id = ((port1 & 0xC0) >> 6) | ((port0 & 0x01) << 2); + fab_id = ((port0 & 0x06) >> 1) + 1; + board_id = port1 & 0x3F; + + CPRINTS("BID:0x%x, FID:0x%x, BOM:0x%x", board_id, fab_id, bom_id); + + return board_id | (fab_id << 8); +} + +#ifdef CONFIG_BOARD_PRE_INIT +/* + * Used to enable JTAG debug during development. + * NOTE: UART2_TX on the same pin as SWV(JTAG_TDO). + * If UART2 is used for EC console you cannot enable SWV. + * For no SWV change mode to MCHP_JTAG_MODE_SWD. + * For low power idle testing enable GPIO060 as function 2(48MHZ_OUT) + * to check PLL is turning off in heavy sleep. Note, do not put GPIO060 + * in gpio.inc + * GPIO060 is port 1 bit[16]. + */ +void board_config_pre_init(void) +{ +#ifdef CONFIG_CHIPSET_DEBUG + MCHP_EC_JTAG_EN = MCHP_JTAG_ENABLE + MCHP_JTAG_MODE_SWD; +#endif + +#if defined(CONFIG_LOW_POWER_IDLE) && defined(CONFIG_MCHP_48MHZ_OUT) + gpio_set_alternate_function(1, 0x10000, 2); +#endif +} +#endif /* #ifdef CONFIG_BOARD_PRE_INIT */ + + +/* + * enable_input_devices() is called by the tablet_mode ISR, but changes the + * state of GPIOs, so its definition must reside after including gpio_list. + */ +static void enable_input_devices(void); +DECLARE_DEFERRED(enable_input_devices); + +void tablet_mode_interrupt(enum gpio_signal signal) +{ + hook_call_deferred(&enable_input_devices_data, 0); +} + +/* SPI devices */ +const struct spi_device_t spi_devices[] = { + { QMSPI0_PORT, 4, GPIO_QMSPI_CS0}, +}; +const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); + +/* + * Enable or disable input devices, + * based upon chipset state and tablet mode + */ +static void enable_input_devices(void) +{ + int kb_enable = 1; + int tp_enable = 1; + + /* Disable both TP and KB in tablet mode */ + if (!gpio_get_level(GPIO_TABLET_MODE_L)) + kb_enable = tp_enable = 0; + /* Disable TP if chipset is off */ + else if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) + tp_enable = 0; + + keyboard_scan_enable(kb_enable, KB_SCAN_DISABLE_LID_ANGLE); + gpio_set_level(GPIO_ENABLE_TOUCHPAD, tp_enable); +} + +#ifdef CONFIG_USBC_VCONN +void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) +{ +#ifndef CONFIG_USBC_PPC_VCONN + /* + * TODO: MCHP EC does not have built-in TCPC. Does external + * I2C based TCPC need this? + */ +#endif +} +#endif + diff --git a/board/sklrvp_mchp/board.h b/board/sklrvp_mchp/board.h new file mode 100644 index 0000000000..faa3b39c66 --- /dev/null +++ b/board/sklrvp_mchp/board.h @@ -0,0 +1,312 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * Intel SKL RVP3 fly wired to MEC152x EVB board-specific configuration + * Microchip Evaluation Board (EVB) with + * MEC15211H 144-pin processor card. + * SKL RVP3 has Kabylake silicon. + */ + +#ifndef __CROS_EC_BOARD_H +#define __CROS_EC_BOARD_H + +/* + * Use UART2 for EC console + */ +#undef CONFIG_UART_CONSOLE +#define CONFIG_UART_CONSOLE 0 + +/* + * Initial board bring-up and prevent power button task from + * generating event to exit G3 state. + */ +/* #define CONFIG_BRINGUP */ + +/* + * Debug on EVB with CONFIG_CHIPSET_DEBUG + * Keep WDG disabled and JTAG enabled. + * CONFIG_BOARD_PRE_INIT enables JTAG early + * #define CONFIG_CHIPSET_DEBUG + */ + +#ifdef CONFIG_CHIPSET_DEBUG +#ifndef CONFIG_BOARD_PRE_INIT +#define CONFIG_BOARD_PRE_INIT +#endif +#endif + +/* + * DEBUG: Add CRC32 in last 4 bytes of EC_RO/RW binaries + * in SPI. LFW will use DMA CRC32 HW to check data integrity. + * #define CONFIG_MCHP_LFW_DEBUG + */ + + +/* + * Override Boot-ROM JTAG mode + * 0x01 = 4-pin standard JTAG + * 0x03 = ARM 2-pin SWD + 1-pin SWV + * 0x05 = ARM 2-pin SWD no SWV. Required if UART2 is used. + */ +/* #define CONFIG_MCHP_JTAG_MODE 0x05 */ + +/* debug MCHP eSPI */ +/* #define CONFIG_ESPI_DEBUG */ + +/* + * Enable Trace FIFO Debug port + * When this is undefined all TRACEn() and tracen() + * macros are defined as blank. + * Uncomment this define to enable these messages. + * Only enable if GPIO's 0171 & 0171 are available therefore + * define this at the board level. + */ +/* #define CONFIG_MCHP_TFDP */ + +/* + * Enable MCHP specific GPIO EC UART commands + * for debug. + */ +/* #define CONFIG_MEC_GPIO_EC_CMDS */ + +/* + * Enable CPRINT in chip eSPI module + * and EC UART test command. + */ +/* #define CONFIG_MCHP_ESPI_DEBUG */ + +/* + * DEBUG + * Disable ARM Cortex-M4 write buffer so + * exceptions become synchronous. + * + * #define CONFIG_DEBUG_DISABLE_WRITE_BUFFER + */ + +/* + * DEBUG: Configure MEC152x GPIO060 as 48MHZ_OUT to + * verify & debug clock is shutdown in heavy sleep. + */ +/* #define CONFIG_MCHP_48MHZ_OUT */ + +/* + * EVB eSPI test mode (no eSPI master connected) + * #define EVB_NO_ESPI_TEST_MODE + */ + +/* + * Enable board specific ISR on ALL_SYS_PWRGD signal. + * Requires for handling Kabylake/Skylake RVP3 board's + * ALL_SYS_PWRGD signal. + */ +#define CONFIG_BOARD_EC_HANDLES_ALL_SYS_PWRGD + +/* + * Maximum clock frequence eSPI EC slave advertises + * Values in MHz are 20, 25, 33, 50, and 66 + */ +/* SKL/KBL + EVB fly-wire hook up only supports 20MHz */ +#define CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ 20 + + +/* + * EC eSPI slave advertises IO lanes + * 0 = Single + * 1 = Single and Dual + * 2 = Single and Quad + * 3 = Single, Dual, and Quad + */ +/* KBL + EVB fly-wire hook up only support Single mode */ +#define CONFIG_HOSTCMD_ESPI_EC_MODE 0 + +/* + * Bit map of eSPI channels EC advertises + * bit[0] = 1 Peripheral channel + * bit[1] = 1 Virtual Wire channel + * bit[2] = 1 OOB channel + * bit[3] = 1 Flash channel + */ +#define CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP 0x0F + +/* MCHP EC variant */ +#define VARIANT_INTELRVP_EC_MCHP + +/* MECC config */ +#define CONFIG_INTEL_RVP_MECC_VERSION_0_9 + +/* USB MUX */ +#define CONFIG_USB_MUX_VIRTUAL + +/* Not using EC FAN control */ +#undef CONFIG_FANS +#define BOARD_FAN_MIN_RPM 3000 +#define BOARD_FAN_MAX_RPM 10000 + +/* Temperature sensor module has dependency on EC fan control */ +#undef CONFIG_TEMP_SENSOR + +#include "baseboard.h" + +/* + * Configuration after inclusion of base board. + * baseboard enables CONFIG_LOW_POWER_IDLE. + * Disable here. + * #undef CONFIG_LOW_POWER_IDLE + */ + +#define CONFIG_CHIPSET_SKYLAKE +#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD +#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_L +#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L +#define GPIO_BAT_LED_RED_L GPIO_BAT_LED_GREEN_L +#define GPIO_PWR_LED_WHITE_L GPIO_AC_LED_GREEN_L +/* MEC152x EVB pin used to enable SKL fan(s) */ +#define GPIO_FAN_POWER_EN GPIO_EC_FAN1_PWM + + +/* Charger */ +#define CONFIG_CHARGER_ISL9241 + +/* DC Jack charge ports */ +#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT +#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1 + +/* USB ports */ +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define DEDICATED_CHARGE_PORT 2 + +#ifdef CONFIG_USBC_VCONN + #define CONFIG_USBC_VCONN_SWAP + /* delay to turn on/off vconn */ + #define PD_VCONN_SWAP_DELAY 5000 /* us */ +#endif + +/* + * USB PD configuration using FUSB307 chip on I2C as + * an example. + */ +#define CONFIG_USB_PD_DUAL_ROLE +#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE +#define CONFIG_USB_PD_TCPM_FUSB307 +#define CONFIG_USB_PD_TCPM_TCPCI + +/* + * MEC152x I2C controllers are multi-port. + * Each controller can use any of the 11 ports. + */ +#define I2C_CONTROLLER_COUNT 4 +#define I2C_PORT_COUNT 4 + +#define I2C_PORT_CHARGER MCHP_I2C_PORT2 +#define I2C_PORT_BATTERY MCHP_I2C_PORT2 +#define I2C_PORT_PCA9555_BOARD_ID_GPIO MCHP_I2C_PORT2 +#define I2C_PORT_PORT80 MCHP_I2C_PORT2 +#define I2C_ADDR_PCA9555_BOARD_ID_GPIO 0x22 +#define PORT80_I2C_ADDR MAX695X_I2C_ADDR1_FLAGS + +/* + * External parallel crystal between XTAL1 and XTAL2 pins. + * #define CONFIG_CLOCK_SRC_EXTERNAL + * #define CONFIG_CLOCK_CRYSTAL + * External single ended 32KHz 50% duty cycle input clock. + * #define CONFIG_CLOCK_SRC_EXTERNAL + * #undef CONFIG_CLOCK_CRYSTAL + * Use internal silicon 32KHz oscillator + * #undef CONFIG_CLOCK_SRC_EXTERNAL + * CONFIG_CLOCK_CRYSTAL is a don't care + * + * +#define CONFIG_CLOCK_SRC_EXTERNAL +*/ +#undef CONFIG_CLOCK_SRC_EXTERNAL +#define CONFIG_CLOCK_CRYSTAL + +/* + * MEC1521H loads firmware using QMSPI controller + * CONFIG_SPI_FLASH_PORT is the index into + * spi_devices[] in board.c + */ +#define CONFIG_SPI_FLASH_PORT 0 +#define CONFIG_SPI_FLASH +/* + * Google uses smaller flashes on chromebook boards + * MCHP SPI test dongle for EVB uses 16MB W25Q128F + * Configure for smaller flash is OK for testing except + * for SPI flash lock bit. + */ + #define CONFIG_FLASH_SIZE_BYTES 524288 + #define CONFIG_SPI_FLASH_W25X40 + +/* + * Enable extra SPI flash and generic SPI + * commands via EC UART + */ +#define CONFIG_CMD_SPI_FLASH +#define CONFIG_CMD_SPI_XFER + + +/* MEC152x does not have GP-SPI controllers */ +#undef CONFIG_MCHP_GPSPI + + +#ifndef __ASSEMBLER__ + +/* #include "gpio_signal.h" */ +/* #include "registers.h" */ + + +enum sklrvp_charge_ports { + TYPE_C_PORT_0, + TYPE_C_PORT_1, +}; + +enum sklrvp_i2c_channel { + I2C_CHAN_BATT_CHG, + I2C_CHAN_MISC, + I2C_CHAN_TCPC_0, + I2C_CHAN_TCPC_1, + I2C_CHAN_COUNT, +}; + +enum battery_type { + BATTERY_SIMPLO_SMP_HHP_408, + BATTERY_SIMPLO_SMP_CA_445, + BATTERY_TYPE_COUNT, +}; + +/* Map I2C port to controller */ +int board_i2c_p2c(int port); + +/* Return the two slave addresses the specified + * controller will respond to when controller + * is acting as a slave. + * b[6:0] = b[7:1] of I2C address 1 + * b[14:8] = b[7:1] of I2C address 2 + */ +uint16_t board_i2c_slave_addrs(int controller); + +/* Reset PD MCU */ +void board_reset_pd_mcu(void); + +#ifdef CONFIG_LOW_POWER_IDLE +void board_prepare_for_deep_sleep(void); +void board_resume_from_deep_sleep(void); +#endif + +#ifdef CONFIG_BOARD_EC_HANDLES_ALL_SYS_PWRGD +void board_all_sys_pwrgd_interrupt(enum gpio_signal signal); +#endif + +int board_get_version(void); + +/* MCHP we need to define this for use by baseboard */ +#define PD_MAX_POWER_MW 60000 + +#endif /* !__ASSEMBLER__ */ + +#endif /* __CROS_EC_BOARD_H */ diff --git a/board/sklrvp_mchp/build.mk b/board/sklrvp_mchp/build.mk new file mode 100644 index 0000000000..81d62ff652 --- /dev/null +++ b/board/sklrvp_mchp/build.mk @@ -0,0 +1,19 @@ +# -*- makefile -*- +# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Intel SKL-RVP fly wired to MEC152x EVB board-specific configuration +# + +# the IC is Microchip MEC1521 +# external SPI is 512KB +# external clock is crystal +CHIP:=mchp +CHIP_FAMILY:=mec152x +CHIP_VARIANT:=mec1521 +CHIP_SPI_SIZE_KB:=512 +BASEBOARD:=intelrvp + +board-y=board.o +board-$(CONFIG_BATTERY_SMART)+=battery.o diff --git a/board/sklrvp_mchp/ec.tasklist b/board/sklrvp_mchp/ec.tasklist new file mode 100644 index 0000000000..b264f6522a --- /dev/null +++ b/board/sklrvp_mchp/ec.tasklist @@ -0,0 +1,25 @@ +/* + * Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * Intel SKL-RVP MCHP MEC152x EVB board-specific configuration. + * See CONFIG_TASK_LIST in config.h for details. + */ + +#define CONFIG_TASK_LIST \ + TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE) + diff --git a/board/sklrvp_mchp/gpio.inc b/board/sklrvp_mchp/gpio.inc new file mode 100644 index 0000000000..164d2f16f4 --- /dev/null +++ b/board/sklrvp_mchp/gpio.inc @@ -0,0 +1,365 @@ +/* -*- mode:c -*- + * + * Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * mec152x EVB board GPIO pins + * !!!!!!!!!!!!!!!!!!!!!!! IMPORTANT !!!!!!!!!!!!!!!!!!!!!!!!!!!! + * MEC152X data sheets GPIO numbers are OCTAL. + * Original glados MEC1322 used these octal numbers as base 10. + * mec152X and its boards will use OCTAL therefore make sure all + * numbers used below are written as C OCTAL with a leading 0. + * Signal names are based upon the MEC152x MECC schematic. + * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + * + */ +/* NOTE: MEC152XH MECC JTAG + * GPIO_0145 is JTAG_TDI + * GPIO_0146 is JTAG_TDO + * GPIO_0147 is JTAG_CLK + * GPIO_0150 is JTAG_TMS + */ +/* NOTE: MEC152X QMSPI controller pins + * MEC152X implements one instance of QMSPI and one + * instance of SLV_SPI. It does not have the GP-SPI + * controllers that MEC1701 has. + * MEC152X QMSPI has three groups of pins that can be + * connected to QMSPI controller. + * PVT_CS#,IO0,IO1,IO2,IO3,CLK + * SHD_CS0#,CS1#,IO0,IO1,IO2,IO3,CLK + * GPSPI_CS#,IO0,IO1,IO2,IO3,CLK + * MEC152X EVB and MECC boards connect their external SPI flash + * to SHD_xxx QMSPI pins. This assumes the part's OTP and straps + * set to not force BootROM load from PVT_xxx SPI port. + * PVT_xxx and GPSPI_xxx are available other uses. + */ +/* NOTE: MEC152xH-SZ unimplemented GPIO pins. + * All MEC152x parts: 041, 0103, 0110, 0164 + * MEC1521H-SZ: 0213, 0211, 0212 + */ + +#define GPIO_BOTH_EDGES_PU (GPIO_INT_BOTH | GPIO_PULL_UP) +#define GPIO_KB_OUTPUT_COL2 (GPIO_OUT_LOW) + +/* MEC152x is eSPI only !!! + * MEC1521 MECC board GPIO_064 PCI_nRESET pulled high to VTR3. + * No signal connection possible. + */ + +GPIO_INT(LID_OPEN, PIN(015), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt) + + +GPIO_INT(AC_PRESENT, PIN(014), GPIO_INT_BOTH, extpower_interrupt) + +/* DC jack handled by intelrvp base board */ +GPIO_INT(DC_JACK_PRESENT, PIN(0244), GPIO_INT_BOTH, board_dc_jack_interrupt) + +/* Buffered power button input from PMIC / ROP_EC_PWR_BTN_L_R */ +GPIO_INT(POWER_BUTTON_L, PIN(023), GPIO_INT_BOTH, power_button_interrupt) + +/* RSMRST from PMIC */ +GPIO_INT(RSMRST_L_PGOOD, PIN(0126), GPIO_INT_BOTH, power_signal_interrupt) + +GPIO_INT(PCH_SLP_SUS_L, PIN(0175), GPIO_INT_BOTH, power_signal_interrupt) + +/* + * Handle ALL_SYS_PWRGD from SKL RVP3 board + * MEC1521H-SZ GPIO_057/VCC_PWRGD OK + */ +GPIO_INT(ALL_SYS_PWRGD, PIN(057), GPIO_INT_BOTH, board_all_sys_pwrgd_interrupt) + +/* Kabylake bring up move to ordinary GPIO input */ +/* MEC1521H-SZ GPIO_0034/GPSPI_IO2 OK */ +/* + *GPIO_INT(VOLUME_UP_L, PIN(034), \ + *GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) + */ +/* MEC1521H-SZ GPIO_035/PWM8/CTOUT1/ICT15 OK */ +/* + *GPIO_INT(VOLUME_DOWN_L, PIN(035), GPIO_INT_BOTH | GPIO_PULL_UP, \ + * button_interrupt) + */ + +/* MEC1521H-SZ GPIO_0161/VCI_IN2# OK */ +GPIO_INT(PMIC_INT_L, PIN(0161), GPIO_INT_FALLING, power_signal_interrupt) + + /* MEC1521H-SZ GPIO_0162/VCI_IN1# OK */ +GPIO_INT(TABLET_MODE_L, PIN(0100), GPIO_INT_BOTH | GPIO_PULL_UP, \ + gmr_tablet_switch_isr) + +/* Delayed PWR_OK from PMIC */ +GPIO_INT(PMIC_DPWROK, PIN(0151), GPIO_INT_BOTH, power_signal_interrupt) + +/* UART input */ +/* MEC1521H-SZ UART0 pins are shared with MCHP TFDP. + * UART1 has one pin used as a Boot-ROM strap. + * UART2_RX is GPIO_0145/I2C09_SDA/JTAG_TDI/UART2_RX + * UART2_TX is GPIO_0146/I2C09_SCL/JTAG_TDO/UART2_TX + * We use ARM SWD on JTAG_TCK and JTAG_TMS freeing up UART2 pins. + */ +GPIO_INT(UART0_RX, PIN(0105), GPIO_INT_BOTH_DSLEEP | GPIO_PULL_UP, \ + uart_deepsleep_interrupt) + +GPIO_INT(USB_C0_VBUS_INT, PIN(0101), GPIO_INT_BOTH, tcpc_alert_event) +GPIO_INT(USB_C1_VBUS_INT, PIN(0102), GPIO_INT_BOTH, tcpc_alert_event) + +/* GPIO Pins not interrupt enabled */ + +/* Kabylake bring up move to ordinary GPIO input */ +GPIO(VOLUME_UP_L, PIN(034), GPIO_INPUT | GPIO_PULL_UP) +GPIO(VOLUME_DOWN_L, PIN(035), GPIO_INPUT | GPIO_PULL_UP) +GPIO(WP_L, PIN(036), GPIO_INPUT) + +/* PCH and CPU pins */ + +/* + * This pull down should be removed and SLP_S0 should be enabled as a power + * signal interrupt in future hardware followers. The signal is pulled up + * in the SoC when the primary rails are on and/or ramping. + * In order to not get interrupt storms there should be external logic + * which makes this a true binary signal into the EC. + */ +GPIO(PCH_SLP_S0_L, PIN(0222), GPIO_INPUT | GPIO_PULL_DOWN) +GPIO(PCH_PWRBTN_L, PIN(043), GPIO_OUTPUT) +GPIO(PCH_SEC_DISABLE_L, PIN(022), GPIO_OUT_HIGH) + +GPIO(PCH_WAKE_L, PIN(0255), GPIO_ODR_HIGH) +GPIO(PCH_ACOK, PIN(0246), GPIO_OUT_LOW) +GPIO(PCH_RSMRST_L, PIN(012), GPIO_OUT_LOW) +GPIO(PCH_RTCRST, PIN(052), GPIO_OUT_LOW) + +GPIO(CPU_PROCHOT, PIN(0171), GPIO_OUT_LOW) + +GPIO(SYS_RESET_L, PIN(025), GPIO_OUT_LOW) + +GPIO(PMIC_SLP_SUS_L, PIN(033), GPIO_OUT_LOW) + +GPIO(EC_PCH_DSW_PWROK, PIN(013), GPIO_OUT_LOW) + +/* + * BATLOW_L and ROP_LDO_EN are stuffing options. Set as input to + * dynamically handle the stuffing option based on board id. + * As both signals have external pulls setting this pin as input + * won't harm anything. + */ +/* MEC1521H-SZ GPIO_0163/VCI_IN0# OK */ +GPIO(BATLOW_L_PMIC_LDO_EN, PIN(0163), GPIO_INPUT) + +/* I2C pins - these will be reconfigured for alternate function below */ +/* MEC1521H-SZ does not implement I2C08 pins */ +GPIO(SMB00_SCL, PIN(004), GPIO_INPUT) +GPIO(SMB00_SDA, PIN(003), GPIO_INPUT) +GPIO(SMB01_SCL, PIN(0131), GPIO_INPUT) +GPIO(SMB01_SDA, PIN(0130), GPIO_INPUT) +GPIO(SMB02_SCL, PIN(0155), GPIO_INPUT) +GPIO(SMB02_SDA, PIN(0154), GPIO_INPUT) +GPIO(SMB03_SCL, PIN(010), GPIO_INPUT) +GPIO(SMB03_SDA, PIN(007), GPIO_INPUT) +GPIO(SMB04_SCL, PIN(0144), GPIO_INPUT) +GPIO(SMB04_SDA, PIN(0143), GPIO_INPUT) +GPIO(SMB05_SCL, PIN(0142), GPIO_INPUT) +GPIO(SMB05_SDA, PIN(0141), GPIO_INPUT) + +/* usb related */ +GPIO(EN_PP3300_A, PIN(0153), GPIO_OUT_LOW) +GPIO(EN_PP5000, PIN(042), GPIO_OUT_LOW) +GPIO(USB_C0_SRC_EN, PIN(0206), GPIO_OUT_LOW) +GPIO(USB_C0_SNK_EN_L, PIN(0202), GPIO_ODR_LOW | GPIO_PULL_DOWN) +GPIO(USB_C0_SRC_HI_ILIM, PIN(0205), GPIO_OUT_LOW) +GPIO(USB_C1_SRC_EN, PIN(0226), GPIO_OUT_LOW) +GPIO(USB_C1_SNK_EN_L, PIN(0140), GPIO_ODR_LOW | GPIO_PULL_DOWN) +GPIO(USB_C1_SRC_HI_ILIM, PIN(0132), GPIO_OUT_LOW) + + +/* Fan PWM output and TACH input. PROCHOT input */ +GPIO(EC_FAN1_TTACH, PIN(050), GPIO_INPUT | GPIO_PULL_UP) +/* Fan PWM output - NC / testing only */ +GPIO(EC_FAN1_PWM, PIN(053), GPIO_OUT_LOW) + +/* prochot input from devices */ +GPIO(PLATFORM_EC_PROCHOT, PIN(051), GPIO_INPUT | GPIO_PULL_UP) + +/* Miscellaneous */ +GPIO(PWM_KBLIGHT, PIN(02), GPIO_OUT_LOW) +GPIO(ENTERING_RW, PIN(0221), GPIO_OUT_LOW) +GPIO(ENABLE_TOUCHPAD, PIN(0115), GPIO_OUT_LOW) +GPIO(EC_BATT_PRES_L, PIN(0200), GPIO_INPUT) +GPIO(WLAN_OFF_L, PIN(0245), GPIO_OUT_LOW) + +/* From lid sensor */ +GPIO(ENABLE_BACKLIGHT, PIN(00), GPIO_OUT_LOW) + +/* Board Version */ +GPIO(BOARD_VERSION1, PIN(0114), GPIO_INPUT) +GPIO(BOARD_VERSION2, PIN(0207), GPIO_INPUT) +GPIO(BOARD_VERSION3, PIN(0011), GPIO_INPUT) + + +/* SPI + * Chip select must be open drain and driven high before SPI controller + * configuration. + */ +/* + * MEC1521H-SZ + * GPIO_0055/PWM2/SHD_CS0#/RSMRST# + * GPIO_0056/PWM3/SHD_CLK + * GPIO_0223/SHD_IO0 + * GPIO_0224/GPTP_IN0/SHD_IO1 + * GPIO_0227/SHD_IO2[PWRGD_STRAP] + * GPIO_0016/GPTP_IN1/SHD_IO3/ICT3(DSW_PWROK) + * + * QMSPI controller drives chip select, must be + * configured to alternative function. See below. + * Always use the name QMSPI_CS0 for chip select. + */ +GPIO(QMSPI_CS0, PIN(055), GPIO_ODR_HIGH) + +GPIO(BAT_LED_GREEN_L, PIN(0156), GPIO_OUT_HIGH) +GPIO(AC_LED_GREEN_L, PIN(0157), GPIO_OUT_HIGH) + +/* Used in baseboard/intelrvp */ +/* GPIO_0253 on EVB JP24-13. Jumper JP24 13-14 for 100K pull-up to Vbat */ +GPIO(EC_SPI_OE_N, PIN(0253), GPIO_OUT_LOW) + +/* Alternate functions GPIO definitions */ + +/* KB pins */ +#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP) +#define GPIO_KB_OUTPUT (GPIO_ODR_HIGH) + +#if defined(CONFIG_CLOCK_SRC_EXTERNAL) && !defined(CONFIG_CLOCK_CRYSTAL) +/* 32KHZ_IN = GPIO_0165(Bank=3, bit=21) Func1 */ +ALTERNATE(PIN_MASK(3, 0x200000), 1, MODULE_PMU, 0) +#endif + +/* + * UART0 + * GPIO_0105 Func 1 = UART_RX + * GPIO_0104 Func 1 = UART_TX + * Bank 2 bits[5:4] + */ +ALTERNATE(PIN_MASK(2, 0x30), 1, MODULE_UART, 0) + +/* KB pins */ +/* + * MEC1521H-SZ (144 pin package) + * KSO00 = GPIO_0040 Func2 bank 1 bit 0 + * KSO01 = GPIO_0045 Func1 bank 1 bit 5 + * KSO02 = GPIO_0046 Func1 bank 1 bit 6 + * KSO03 = GPIO_0047 Func1 bank 1 bit 7 + * KSO04 = GPIO_0107 Func2 bank 2 bit 7 + * KSO05 = GPIO_0112 Func1 bank 2 bit 10 + * KSO06 = GPIO_0113 Func1 bank 2 bit 11 + * KSO07 = GPIO_0120 Func1 bank 2 bit 16 + * KSO08 = GPIO_0121 Func2 bank 2 bit 17 + * KSO09 = GPIO_0122 Func2 bank 2 bit 18 + * KSO10 = GPIO_0123 Func2 bank 2 bit 19 + * KSO11 = GPIO_0124 Func2 bank 2 bit 20 + * KSO12 = GPIO_0125 Func2 bank 2 bit 21 + * For 8x16 test keyboard add KSO13 - KSO15 + * KSO13 = GPIO_0126 Func2 bank 2 bit 22 + * KSO14 = GPIO_0152 Func1 bank 3 bit 10 + * KSO15 = GPIO_0151 Func2 bank 3 bit 9 + * + * KSI0 = GPIO_0017 Func1 bank 0 bit 15 + * KSI1 = GPIO_0020 Func1 bank 0 bit 16 + * KSI2 = GPIO_0021 Func1 bank 0 bit 17 + * KSI3 = GPIO_0026 Func1 bank 0 bit 22 + * KSI4 = GPIO_0027 Func1 bank 0 bit 23 + * KSI5 = GPIO_0030 Func1 bank 0 bit 24 + * KSI6 = GPIO_0031 Func1 bank 0 bit 25 + * KSI7 = GPIO_0032 Func1 bank 0 bit 26 + */ +/* KSO 0 Bank 1, Func2, bit 0 */ +ALTERNATE(PIN_MASK(1, 0x01), 2, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT) + +#ifdef CONFIG_KEYBOARD_COL2_INVERTED +/* KSO 1-3 Bank 1, Func1, bits 5-7 */ +ALTERNATE(PIN_MASK(1, 0xA0), 1, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT) +GPIO(KBD_KSO2, PIN(046), GPIO_KB_OUTPUT_COL2) +#else +/* KSO 1-3 Bank 1, Func1, bits 5-7 */ +ALTERNATE(PIN_MASK(1, 0xE0), 1, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT) +#endif + +/* KSO 4, 8-12 Bank 2, Func2, bits 7, 17-21 */ +ALTERNATE(PIN_MASK(2, 0x003E0080), 2, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT) +/* KSO 5-7, Bank 2, Func1, bits 10-11, 16 */ +ALTERNATE(PIN_MASK(2, 0x00010C00), 1, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT) + +/* KSI 0-7, Bank 0, Func1, bit 15-17, 22-26 */ +ALTERNATE(PIN_MASK(0, 0x07C38000), 1, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) + +/* + * ESPI_RESET# - GPIO_0061 Func 1, Bank 1 bit[17] + * ESPI_ALERT# - GPIO_0063 Func 1, Bank 1 bit[19] + * ESPI_CLK - GPIO_0065 Func 1, Bank 1 bit[21] + * ESPI_CS# - GPIO_0066 Func 1, Bank 1 bit[22] + * ESPI_IO0 - GPIO_0070 Func 1, Bank 1 bit[24] + * ESPI_IO1 - GPIO_0071 Func 1, Bank 1 bit[25] + * ESPI_IO2 - GPIO_0072 Func 1, Bank 1 bit[26] + * ESPI_IO3 - GPIO_0073 Func 1, Bank 1 bit[27] + */ +ALTERNATE(PIN_MASK(1, 0x0F6A0000), 1, MODULE_LPC, 0) + +/* MECC card SPI flash is connected to QMSPI Shared Port + * Also, MEC1521H-SZ Private SPI Port (Port 1) has pins multiplexed + * with KSO pins used in key scan! + * QMSPI Shared SPI Port (Port 0) + * NOTE: QMSPI Shared SPI Port pins are on VTR2 + */ +/* + * MEC1521H-SZ MECC board SPI flash is connected to MEC1521H-SZ shared + * SPI port. SHD_nCS is the chip select signal connected to + * GPIO_0055(SHD_CS0#) pin. MECC board has 10K pulls to +3.3V on all + * the board SPI flash signals. MEC152x SHD SPI signals are on the chip's + * VTR2 rail. If VTR2 is connected to 1.8V there could be back drive issues. + * We must set the respective GPIO's to their shared SPI alternate functions. + * Only enable CS0#, CLK, IO0, and IO1 as EC code does not use quad mode. + * NOTE 1: SHD_IO2 is also used a Boot-ROM PWRGD_STRAP. + * NOTE 2: Be very careful re-using SHD_IO2 and SHD_IO3 for other functions. + * SHD_CS0# will be set to open drain drive high. + * SHD_CS0# = GPIO_0055(Bank 1, bit[13]) Func2 + * SHD_CLK = GPIO_0056(Bank 1, bit[14]) Func2 + * SHD_IO0 = GPIO_0223(Bank 4, bit[19]) Func1 + * SHD_IO1 = GPIO_0224(Bank 4, bit[20]) Func2 + * SHD_IO2 = GPIO_0227(Bank 4, bit[23]) Func1 + * SHD_IO3 = GPIO_0016(Bank 0, bit[14]) Func2 + */ +ALTERNATE(PIN_MASK(1, 0x2000), 2, MODULE_SPI_FLASH, GPIO_ODR_HIGH) +ALTERNATE(PIN_MASK(1, 0x4000), 2, MODULE_SPI_FLASH, 0) +ALTERNATE(PIN_MASK(4, 0x00080000), 1, MODULE_SPI_FLASH, 0) +ALTERNATE(PIN_MASK(4, 0x00100000), 2, MODULE_SPI_FLASH, 0) + +/* I2C pins */ +/* MEC1521H-SZ does not implement I2C08 pins + * Configure I2C00-05 as I2C alternate function + * I2C00_SDA = GPIO_0003(Bank=0, bit=3) Func1 + * I2C00_SCL = GPIO_0004(Bank=0, bit=4) Func1 + * I2C01_SDA = GPIO_0130(Bank=2, bit=24) Func1 + * I2C01_SCL = GPIO_0131(Bank=2, bit=25) Func1 + * I2C02_SDA = GPIO_0154(Bank=3, bit=12) Func1 + * I2C02_SCL = GPIO_0155(Bank=3, bit=13) Func1 + * I2C03_SDA = GPIO_0007(Bank=0, bit=7) Func1 + * I2C03_SDL = GPIO_0010(Bank=0, bit=8) Func1 + * I2C04_SDA = GPIO_0143(Bank=3, bit=3) Func1 + * I2C04_SCL = GPIO_0144(Bank=3, bit=4) Func1 + * I2C05_SDA = GPIO_0141(Bank=3, bit=1) Func1 + * I2C05_SDL = GPIO_0142(Bank=3, bit=2) Func1 + */ +/* DEBUG with MECC not connected to motherboard. Enable internal pull-ups on I2C pins */ +ALTERNATE(PIN_MASK(0, 0x00000198), 1, MODULE_I2C, GPIO_ODR_HIGH) +ALTERNATE(PIN_MASK(2, 0x03000000), 1, MODULE_I2C, GPIO_ODR_HIGH) +ALTERNATE(PIN_MASK(3, 0x0000301E), 1, MODULE_I2C, GPIO_ODR_HIGH) + +/* ADC pins */ +/* ADC01 = GPIO_0201(Bank=4, bit=1) Func1 + * ADC03 = GPIO_0203(Bank=4, bit=3) Func1 + * ADC04 = GPIO_0204(Bank=4, bit=4) Func1 + * ADC07 = GPIO_0207/CMP_STRAP(Bank=4, bit=7) Func1 + */ +ALTERNATE(PIN_MASK(4, 0x009a), 1, MODULE_ADC, GPIO_ANALOG) + diff --git a/board/sklrvp_mchp/lfw/gpio.inc b/board/sklrvp_mchp/lfw/gpio.inc new file mode 100644 index 0000000000..e969e4d09c --- /dev/null +++ b/board/sklrvp_mchp/lfw/gpio.inc @@ -0,0 +1,41 @@ +/* -*- mode:c -*- + * + * Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Minimal set of GPIOs needed for LFW loader + */ + +/* + * MEC1701H GPIO_0055/PWM2/SHD_CS0#/RSMRST# + * MEC1701H QMSPI controller drives chip select, must be + * configured to alternative function. See below. + * GPIO_SHD_CS0 is used in board level spi_devices[] table + */ +GPIO(QMSPI_CS0, PIN(055), GPIO_ODR_HIGH) + + +/* Alternate functions GPIO definition */ + +/* + * UART0 + * GPIO_0105 Func 1 = UART_RX + * GPIO_0104 Func 1 = UART_TX + * Bank 2 bits[5:4] + */ +ALTERNATE(PIN_MASK(2, 0x30), 1, MODULE_UART, 0) + +/* SPI pins */ +/* + * MEC1701H SHD SPI is connected to QMSPI controller. + * QMSPI drives chip select. SHD_CS0#(GPIO_0055) must be set + * to alternate function 2 and GPIO_ODR_HIGH. + * GPIO_0055 Function 2, Bank 1 bit[13] + */ +ALTERNATE(PIN_MASK(1, 0x2000), 2, MODULE_SPI_FLASH, GPIO_ODR_HIGH) +/* SHD_CLK - GPIO_0056 Function 2, Bank 1 bit[14] */ +ALTERNATE(PIN_MASK(1, 0x4000), 2, MODULE_SPI_FLASH, 0) +/* MOSI(SHD_IO0) - GPIO_0223 Function 2, Bank 4 bit[19] */ +/* MISO(SHD_IO1) - GPIO_0224 Function 2, Bank 4 bit[20] */ +ALTERNATE(PIN_MASK(4, 0x180000), 2, MODULE_SPI_FLASH, 0) |