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authorAnton Staaf <robotboy@chromium.org>2014-06-24 07:52:49 -0700
committerchrome-internal-fetch <chrome-internal-fetch@google.com>2014-06-26 02:43:01 +0000
commit9ccfd4553e708a5df4be3aa18b97c75da3f6c1b9 (patch)
treebd10678c7ee25901de97260967b8bee4a849baa5 /board/squawks
parent88c0ffd692b4e6d5fadc75bb15255e0684d6a1c9 (diff)
downloadchrome-ec-9ccfd4553e708a5df4be3aa18b97c75da3f6c1b9.tar.gz
gpio: Replace duplication in gpio declarations with X-macro file
Previously each board.h and board.c contained an enum and an array for gpio definitons that had to be manually kept in sync, with no compiler assistance other than that their lengths matched. This change adds a single gpio.inc file that declares all gpio's that a board uses and is used as an X-macro include file to generate both the gpio_signal enum and the gpio_list array. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=none TEST=make buildall -j Change-Id: If9c9feca968619a59ff9f20701359bcb9374e4da Reviewed-on: https://chromium-review.googlesource.com/205354 Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
Diffstat (limited to 'board/squawks')
-rw-r--r--board/squawks/board.c82
-rw-r--r--board/squawks/board.h66
-rw-r--r--board/squawks/gpio.inc116
3 files changed, 118 insertions, 146 deletions
diff --git a/board/squawks/board.c b/board/squawks/board.c
index a99bbe24a1..f199e99d3e 100644
--- a/board/squawks/board.c
+++ b/board/squawks/board.c
@@ -32,87 +32,7 @@
#include "uart.h"
#include "util.h"
-/* GPIO signal list. Must match order from enum gpio_signal. */
-const struct gpio_info gpio_list[] = {
- /* Inputs with interrupt handlers are first for efficiency */
- {"POWER_BUTTON_L", LM4_GPIO_A, (1<<2), GPIO_INT_BOTH_DSLEEP,
- power_button_interrupt},
- {"LID_OPEN", LM4_GPIO_A, (1<<3), GPIO_INT_BOTH_DSLEEP,
- lid_interrupt},
- {"AC_PRESENT", LM4_GPIO_H, (1<<3), GPIO_INT_BOTH_DSLEEP,
- extpower_interrupt},
- {"PCH_SLP_S3_L", LM4_GPIO_G, (1<<7), GPIO_INT_BOTH_DSLEEP |
- GPIO_PULL_UP,
- power_signal_interrupt},
- {"PCH_SLP_S4_L", LM4_GPIO_H, (1<<1), GPIO_INT_BOTH_DSLEEP |
- GPIO_PULL_UP,
- power_signal_interrupt},
- {"PP1050_PGOOD", LM4_GPIO_H, (1<<4), GPIO_INT_BOTH,
- power_signal_interrupt},
- {"PP3300_PCH_PGOOD", LM4_GPIO_C, (1<<4), GPIO_INT_BOTH,
- power_signal_interrupt},
- {"PP5000_PGOOD", LM4_GPIO_N, (1<<0), GPIO_INT_BOTH,
- power_signal_interrupt},
- {"S5_PGOOD", LM4_GPIO_G, (1<<0), GPIO_INT_BOTH,
- power_signal_interrupt},
- {"VCORE_PGOOD", LM4_GPIO_C, (1<<6), GPIO_INT_BOTH,
- power_signal_interrupt},
- {"WP_L", LM4_GPIO_A, (1<<4), GPIO_INT_BOTH,
- switch_interrupt},
- {"JTAG_TCK", LM4_GPIO_C, (1<<0), GPIO_DEFAULT,
- jtag_interrupt},
- {"UART0_RX", LM4_GPIO_A, (1<<0), GPIO_INT_BOTH_DSLEEP |
- GPIO_PULL_UP,
- uart_deepsleep_interrupt},
-
- /* Other inputs */
- {"BOARD_VERSION1", LM4_GPIO_Q, (1<<5), GPIO_INPUT, NULL},
- {"BOARD_VERSION2", LM4_GPIO_Q, (1<<6), GPIO_INPUT, NULL},
- {"BOARD_VERSION3", LM4_GPIO_Q, (1<<7), GPIO_INPUT, NULL},
-#ifdef CONFIG_CHIPSET_DEBUG
- {"PCH_SLP_SX_L", LM4_GPIO_G, (1<<3), GPIO_INPUT|GPIO_PULL_UP,
- NULL},
- {"PCH_SUS_STAT_L", LM4_GPIO_G, (1<<6), GPIO_INPUT|GPIO_PULL_UP,
- NULL},
- {"PCH_SUSPWRDNACK", LM4_GPIO_G, (1<<2), GPIO_INPUT|GPIO_PULL_UP,
- NULL},
-#endif
- {"PP1000_S0IX_PGOOD", LM4_GPIO_H, (1<<6), GPIO_INPUT, NULL},
- {"USB1_OC_L", LM4_GPIO_E, (1<<7), GPIO_INPUT, NULL},
- {"USB2_OC_L", LM4_GPIO_E, (1<<0), GPIO_INPUT, NULL},
-
- /* Outputs; all unasserted by default except for reset signals */
- {"CPU_PROCHOT", LM4_GPIO_B, (1<<5), GPIO_OUT_LOW, NULL},
- {"ENABLE_BACKLIGHT", LM4_GPIO_M, (1<<7), GPIO_ODR_HIGH, NULL},
- {"ENABLE_TOUCHPAD", LM4_GPIO_N, (1<<1), GPIO_OUT_LOW, NULL},
- {"ENTERING_RW", LM4_GPIO_D, (1<<6), GPIO_OUT_LOW, NULL},
- {"LPC_CLKRUN_L", LM4_GPIO_M, (1<<2), GPIO_ODR_HIGH, NULL},
- {"PCH_CORE_PWROK", LM4_GPIO_F, (1<<5), GPIO_OUT_LOW, NULL},
- {"PCH_PWRBTN_L", LM4_GPIO_H, (1<<0), GPIO_ODR_HIGH, NULL},
- {"PCH_RCIN_L", LM4_GPIO_F, (1<<3), GPIO_ODR_HIGH, NULL},
- {"PCH_RSMRST_L", LM4_GPIO_F, (1<<1), GPIO_OUT_LOW, NULL},
- {"PCH_SMI_L", LM4_GPIO_F, (1<<4), GPIO_ODR_HIGH, NULL},
- {"PCH_SOC_OVERRIDE", LM4_GPIO_G, (1<<1), GPIO_OUT_LOW, NULL},
- {"PCH_SYS_PWROK", LM4_GPIO_J, (1<<1), GPIO_OUT_LOW, NULL},
- {"PCH_WAKE_L", LM4_GPIO_F, (1<<0), GPIO_ODR_HIGH, NULL},
- {"PP1350_EN", LM4_GPIO_H, (1<<5), GPIO_OUT_LOW, NULL},
- {"PP3300_DX_EN", LM4_GPIO_J, (1<<2), GPIO_OUT_LOW, NULL},
- {"PP3300_LTE_EN", LM4_GPIO_D, (1<<4), GPIO_OUT_LOW, NULL},
- {"PP3300_WLAN_EN", LM4_GPIO_J, (1<<0), GPIO_OUT_LOW, NULL},
- {"PP5000_EN", LM4_GPIO_H, (1<<7), GPIO_OUT_LOW, NULL},
- {"PPSX_EN", LM4_GPIO_L, (1<<6), GPIO_OUT_LOW, NULL},
- {"SUSP_VR_EN", LM4_GPIO_C, (1<<7), GPIO_OUT_LOW, NULL},
- {"TOUCHSCREEN_RESET_L", LM4_GPIO_N, (1<<7), GPIO_OUT_LOW, NULL},
- {"USB_CTL1", LM4_GPIO_E, (1<<6), GPIO_OUT_LOW, NULL},
- {"USB_ILIM_SEL", LM4_GPIO_E, (1<<5), GPIO_OUT_LOW, NULL},
- {"USB1_ENABLE", LM4_GPIO_E, (1<<4), GPIO_OUT_LOW, NULL},
- {"USB2_ENABLE", LM4_GPIO_D, (1<<5), GPIO_OUT_LOW, NULL},
- {"VCORE_EN", LM4_GPIO_C, (1<<5), GPIO_OUT_LOW, NULL},
- {"WLAN_OFF_L", LM4_GPIO_J, (1<<4), GPIO_OUT_LOW, NULL},
- {"PCH_SCI_L", LM4_GPIO_M, (1<<1), GPIO_ODR_HIGH, NULL},
- {"KBD_IRQ_L", LM4_GPIO_M, (1<<3), GPIO_ODR_HIGH, NULL},
-};
-BUILD_ASSERT(ARRAY_SIZE(gpio_list) == GPIO_COUNT);
+#include "gpio_list.h"
/* Pins with alternate functions */
const struct gpio_alt_func gpio_alt_funcs[] = {
diff --git a/board/squawks/board.h b/board/squawks/board.h
index 4a757e793b..935752fdf3 100644
--- a/board/squawks/board.h
+++ b/board/squawks/board.h
@@ -68,71 +68,7 @@
#define WIRELESS_GPIO_WWAN GPIO_PP3300_LTE_EN
#define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_WLAN_EN
-/* GPIO signal definitions. */
-enum gpio_signal {
- /* Inputs with interrupt handlers are first for efficiency */
- GPIO_POWER_BUTTON_L = 0, /* Power button */
- GPIO_LID_OPEN, /* Lid switch */
- GPIO_AC_PRESENT, /* AC power present */
- GPIO_PCH_SLP_S3_L, /* SLP_S3# signal from PCH */
- GPIO_PCH_SLP_S4_L, /* SLP_S4# signal from PCH */
- GPIO_PP1050_PGOOD, /* Power good on 1.05V */
- GPIO_PP3300_PCH_PGOOD, /* Power good on 3.3V (PCH supply) */
- GPIO_PP5000_PGOOD, /* Power good on 5V */
- GPIO_S5_PGOOD, /* Power good on S5 supplies */
- GPIO_VCORE_PGOOD, /* Power good on core VR */
- GPIO_WP_L, /* Write protect input */
- GPIO_JTAG_TCK, /* JTAG clock input */
- GPIO_UART0_RX, /* UART0 RX input */
-
- /* Other inputs */
- GPIO_BOARD_VERSION1, /* Board version stuffing resistor 1 */
- GPIO_BOARD_VERSION2, /* Board version stuffing resistor 2 */
- GPIO_BOARD_VERSION3, /* Board version stuffing resistor 3 */
-#ifdef CONFIG_CHIPSET_DEBUG
- GPIO_PCH_SLP_SX_L, /* SLP_S0IX# signal from PCH */
- GPIO_PCH_SUS_STAT_L, /* SUS_STAT# signal from PCH */
- GPIO_PCH_SUSPWRDNACK, /* SUSPWRDNACK signal from PCH */
-#endif
- GPIO_PP1000_S0IX_PGOOD, /* Power good on 1.00V (S0iX supplies) */
- GPIO_USB1_OC_L, /* USB port overcurrent warning */
- GPIO_USB2_OC_L, /* USB port overcurrent warning */
-
- /* Outputs */
- GPIO_CPU_PROCHOT, /* Force CPU to think it's overheated */
- GPIO_ENABLE_BACKLIGHT, /* Enable backlight power */
- GPIO_ENABLE_TOUCHPAD, /* Enable touchpad power */
- GPIO_ENTERING_RW, /* Indicate when EC is entering RW code */
- GPIO_LPC_CLKRUN_L, /* Request that PCH drive LPC clock */
- GPIO_PCH_CORE_PWROK, /* Indicate core well power is stable */
- GPIO_PCH_PWRBTN_L, /* Power button output to PCH */
- GPIO_PCH_RCIN_L, /* Reset line to PCH (for 8042 emulation) */
- GPIO_PCH_RSMRST_L, /* Reset PCH resume power plane logic */
- GPIO_PCH_SMI_L, /* System management interrupt to PCH */
- GPIO_PCH_SOC_OVERRIDE, /* SOC override signal to PCH; when high, ME
- * ignores security descriptor */
- GPIO_PCH_SYS_PWROK, /* EC thinks everything is up and ready */
- GPIO_PCH_WAKE_L, /* Wake signal from EC to PCH */
- GPIO_PP1350_EN, /* Enable 1.35V supply */
- GPIO_PP3300_DX_EN, /* Enable power to lots of peripherals */
- GPIO_PP3300_LTE_EN, /* Enable LTE radio */
- GPIO_PP3300_WLAN_EN, /* Enable WiFi power */
- GPIO_PP5000_EN, /* Enable 5V supply */
- GPIO_PPSX_EN, /* Enable PP1350_PCH_SX, PP1000_PCH_SX */
- GPIO_SUSP_VR_EN, /* Enable 1.05V regulator */
- GPIO_TOUCHSCREEN_RESET_L, /* Reset touch screen */
- GPIO_USB_CTL1, /* USB control signal 1 to both ports */
- GPIO_USB_ILIM_SEL, /* USB current limit to both ports */
- GPIO_USB1_ENABLE, /* USB port 1 output power enable */
- GPIO_USB2_ENABLE, /* USB port 2 output power enable */
- GPIO_VCORE_EN, /* Enable core power supplies */
- GPIO_WLAN_OFF_L, /* Disable WiFi radio */
- GPIO_PCH_SCI_L, /* Assert SCI to PCH */
- GPIO_KBD_IRQ_L, /* Negative edge triggered irq. */
-
- /* Number of GPIOs; not an actual GPIO */
- GPIO_COUNT
-};
+#include "gpio_signal.h"
/* power signal definitions */
enum power_signal {
diff --git a/board/squawks/gpio.inc b/board/squawks/gpio.inc
new file mode 100644
index 0000000000..51400c7c8e
--- /dev/null
+++ b/board/squawks/gpio.inc
@@ -0,0 +1,116 @@
+/* -*- mode:c -*-
+ *
+ * Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Inputs with interrupt handlers are first for efficiency */
+/* Power button */
+GPIO(POWER_BUTTON_L, A, 2, GPIO_INT_BOTH_DSLEEP, power_button_interrupt)
+/* Lid switch */
+GPIO(LID_OPEN, A, 3, GPIO_INT_BOTH_DSLEEP, lid_interrupt)
+/* AC power present */
+GPIO(AC_PRESENT, H, 3, GPIO_INT_BOTH_DSLEEP, extpower_interrupt)
+/* SLP_S3# signal from PCH */
+GPIO(PCH_SLP_S3_L, G, 7, GPIO_INT_BOTH_DSLEEP | GPIO_PULL_UP, power_signal_interrupt)
+/* SLP_S4# signal from PCH */
+GPIO(PCH_SLP_S4_L, H, 1, GPIO_INT_BOTH_DSLEEP | GPIO_PULL_UP, power_signal_interrupt)
+/* Power good on 1.05V */
+GPIO(PP1050_PGOOD, H, 4, GPIO_INT_BOTH, power_signal_interrupt)
+/* Power good on 3.3V (PCH supply) */
+GPIO(PP3300_PCH_PGOOD, C, 4, GPIO_INT_BOTH, power_signal_interrupt)
+/* Power good on 5V */
+GPIO(PP5000_PGOOD, N, 0, GPIO_INT_BOTH, power_signal_interrupt)
+/* Power good on S5 supplies */
+GPIO(S5_PGOOD, G, 0, GPIO_INT_BOTH, power_signal_interrupt)
+/* Power good on core VR */
+GPIO(VCORE_PGOOD, C, 6, GPIO_INT_BOTH, power_signal_interrupt)
+/* Write protect input */
+GPIO(WP_L, A, 4, GPIO_INT_BOTH, switch_interrupt)
+/* JTAG clock input */
+GPIO(JTAG_TCK, C, 0, GPIO_DEFAULT, jtag_interrupt)
+/* UART0 RX input */
+GPIO(UART0_RX, A, 0, GPIO_INT_BOTH_DSLEEP | GPIO_PULL_UP, uart_deepsleep_interrupt)
+
+/* Other inputs */
+/* Board version stuffing resistor 1 */
+GPIO(BOARD_VERSION1, Q, 5, GPIO_INPUT, NULL)
+/* Board version stuffing resistor 2 */
+GPIO(BOARD_VERSION2, Q, 6, GPIO_INPUT, NULL)
+/* Board version stuffing resistor 3 */
+GPIO(BOARD_VERSION3, Q, 7, GPIO_INPUT, NULL)
+#ifdef CONFIG_CHIPSET_DEBUG
+/* SLP_S0IX# signal from PCH */
+GPIO(PCH_SLP_SX_L, G, 3, GPIO_INPUT | GPIO_PULL_UP, NULL)
+/* SUS_STAT# signal from PCH */
+GPIO(PCH_SUS_STAT_L, G, 6, GPIO_INPUT | GPIO_PULL_UP, NULL)
+/* SUSPWRDNACK signal from PCH */
+GPIO(PCH_SUSPWRDNACK, G, 2, GPIO_INPUT | GPIO_PULL_UP, NULL)
+#endif
+/* Power good on 1.00V (S0iX supplies) */
+GPIO(PP1000_S0IX_PGOOD, H, 6, GPIO_INPUT, NULL)
+/* USB port overcurrent warning */
+GPIO(USB1_OC_L, E, 7, GPIO_INPUT, NULL)
+/* USB port overcurrent warning */
+GPIO(USB2_OC_L, E, 0, GPIO_INPUT, NULL)
+
+/* Outputs; all unasserted by default except for reset signals */
+/* Force CPU to think it's overheated */
+GPIO(CPU_PROCHOT, B, 5, GPIO_OUT_LOW, NULL)
+/* Enable backlight power */
+GPIO(ENABLE_BACKLIGHT, M, 7, GPIO_ODR_HIGH, NULL)
+/* Enable touchpad power */
+GPIO(ENABLE_TOUCHPAD, N, 1, GPIO_OUT_LOW, NULL)
+/* Indicate when EC is entering RW code */
+GPIO(ENTERING_RW, D, 6, GPIO_OUT_LOW, NULL)
+/* Request that PCH drive LPC clock */
+GPIO(LPC_CLKRUN_L, M, 2, GPIO_ODR_HIGH, NULL)
+/* Indicate core well power is stable */
+GPIO(PCH_CORE_PWROK, F, 5, GPIO_OUT_LOW, NULL)
+/* Power button output to PCH */
+GPIO(PCH_PWRBTN_L, H, 0, GPIO_ODR_HIGH, NULL)
+/* Reset line to PCH (for 8042 emulation) */
+GPIO(PCH_RCIN_L, F, 3, GPIO_ODR_HIGH, NULL)
+/* Reset PCH resume power plane logic */
+GPIO(PCH_RSMRST_L, F, 1, GPIO_OUT_LOW, NULL)
+/* System management interrupt to PCH */
+GPIO(PCH_SMI_L, F, 4, GPIO_ODR_HIGH, NULL)
+/* SOC override signal to PCH; when high, ME ignores security descriptor */
+GPIO(PCH_SOC_OVERRIDE, G, 1, GPIO_OUT_LOW, NULL)
+/* EC thinks everything is up and ready */
+GPIO(PCH_SYS_PWROK, J, 1, GPIO_OUT_LOW, NULL)
+/* Wake signal from EC to PCH */
+GPIO(PCH_WAKE_L, F, 0, GPIO_ODR_HIGH, NULL)
+/* Enable 1.35V supply */
+GPIO(PP1350_EN, H, 5, GPIO_OUT_LOW, NULL)
+/* Enable power to lots of peripherals */
+GPIO(PP3300_DX_EN, J, 2, GPIO_OUT_LOW, NULL)
+/* Enable LTE radio */
+GPIO(PP3300_LTE_EN, D, 4, GPIO_OUT_LOW, NULL)
+/* Enable WiFi power */
+GPIO(PP3300_WLAN_EN, J, 0, GPIO_OUT_LOW, NULL)
+/* Enable 5V supply */
+GPIO(PP5000_EN, H, 7, GPIO_OUT_LOW, NULL)
+/* Enable PP1350_PCH_SX, PP1000_PCH_SX */
+GPIO(PPSX_EN, L, 6, GPIO_OUT_LOW, NULL)
+/* Enable 1.05V regulator */
+GPIO(SUSP_VR_EN, C, 7, GPIO_OUT_LOW, NULL)
+/* Reset touch screen */
+GPIO(TOUCHSCREEN_RESET_L, N, 7, GPIO_OUT_LOW, NULL)
+/* USB control signal 1 to both ports */
+GPIO(USB_CTL1, E, 6, GPIO_OUT_LOW, NULL)
+/* USB current limit to both ports */
+GPIO(USB_ILIM_SEL, E, 5, GPIO_OUT_LOW, NULL)
+/* USB port 1 output power enable */
+GPIO(USB1_ENABLE, E, 4, GPIO_OUT_LOW, NULL)
+/* USB port 2 output power enable */
+GPIO(USB2_ENABLE, D, 5, GPIO_OUT_LOW, NULL)
+/* Enable core power supplies */
+GPIO(VCORE_EN, C, 5, GPIO_OUT_LOW, NULL)
+/* Disable WiFi radio */
+GPIO(WLAN_OFF_L, J, 4, GPIO_OUT_LOW, NULL)
+/* Assert SCI to PCH */
+GPIO(PCH_SCI_L, M, 1, GPIO_ODR_HIGH, NULL)
+/* Negative edge triggered irq. */
+GPIO(KBD_IRQ_L, M, 3, GPIO_ODR_HIGH, NULL)