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| author | Daisuke Nojiri <dnojiri@chromium.org> | 2016-04-26 12:19:35 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-04-29 07:34:52 -0700 |
| commit | 38c93a26f32c49f3cc6aa5ddb057f7a788633bfb (patch) | |
| tree | bde43d2dcaca526f0aa6cec02876ad57d07fd2b4 /board/stm32l476g-eval | |
| parent | 2b79492093935e3fe2aa2117216a819a3974d70b (diff) | |
| download | chrome-ec-38c93a26f32c49f3cc6aa5ddb057f7a788633bfb.tar.gz | |
STM32: Add HSE and PLL to clock source selection
This patch adds HSE and PLL as a system clock oscillator for STM32L4.
This allows us to drive the chip at a higher frequency (up to 80 MHz),
which is necessary to big-bang GPIO ports accurately.
BUG=none
BRANCH=tot
TEST=make buildall. Verified console works on STM32L476G-Eval using HSE,
PLL-HSE, PLL-HSI, PLL-MSI as an oscillator. Verified console runs soundly
with different frequencies from 20 Mhz to 80 Mhz. Verified frequencies
using oscilloscope on MCO (Microcontroller Clock Output) port up to 50 MHz.
Change-Id: I493cdb6c323eb4e6a1560f6d030935c1950b1a2a
Reviewed-on: https://chromium-review.googlesource.com/341275
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'board/stm32l476g-eval')
| -rw-r--r-- | board/stm32l476g-eval/board.h | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/board/stm32l476g-eval/board.h b/board/stm32l476g-eval/board.h index d6f9eb73b2..7ce7875ac6 100644 --- a/board/stm32l476g-eval/board.h +++ b/board/stm32l476g-eval/board.h @@ -40,7 +40,18 @@ #undef CONFIG_FLASH /* Timer selection */ -#define TIM_CLOCK32 5 +#define TIM_CLOCK32 5 + +/* External clock speeds (8 MHz) */ +#define STM32_HSE_CLOCK 8000000 + +/* PLL configuration. Freq = STM32_HSE_CLOCK * n/m/r */ +#undef STM32_PLLM +#define STM32_PLLM 1 +#undef STM32_PLLN +#define STM32_PLLN 10 +#undef STM32_PLLR +#define STM32_PLLR 2 #include "gpio_signal.h" |