diff options
author | Daisuke Nojiri <dnojiri@chromium.org> | 2016-04-20 14:49:56 -0700 |
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committer | chrome-bot <chrome-bot@chromium.org> | 2016-04-25 16:49:02 -0700 |
commit | 40c02e3ff2477df1aca7657a92905816e5a13d0c (patch) | |
tree | 57f05231828259506bf8bfdd2c494e533715e01f /board/stm32l476g-eval | |
parent | cb0d8108e5a5b630ec05a8d21a824cb601246bf5 (diff) | |
download | chrome-ec-40c02e3ff2477df1aca7657a92905816e5a13d0c.tar.gz |
Bring up STM32L476G-Eval
This patch adds initial set of files to bring up STM32L476G-Eval board.
BUG=none
BRANCH=tot
TEST=Tested console. make buildall && make tests
Change-Id: I0c0f73f31e84099746fced4214c5ed7f45468cef
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/340100
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'board/stm32l476g-eval')
l--------- | board/stm32l476g-eval/Makefile | 1 | ||||
-rw-r--r-- | board/stm32l476g-eval/board.c | 20 | ||||
-rw-r--r-- | board/stm32l476g-eval/board.h | 42 | ||||
-rw-r--r-- | board/stm32l476g-eval/build.mk | 12 | ||||
-rw-r--r-- | board/stm32l476g-eval/ec.tasklist | 21 | ||||
-rw-r--r-- | board/stm32l476g-eval/gpio.inc | 19 | ||||
-rw-r--r-- | board/stm32l476g-eval/openocd-flash.cfg | 19 |
7 files changed, 134 insertions, 0 deletions
diff --git a/board/stm32l476g-eval/Makefile b/board/stm32l476g-eval/Makefile new file mode 120000 index 0000000000..94aaae2c4d --- /dev/null +++ b/board/stm32l476g-eval/Makefile @@ -0,0 +1 @@ +../../Makefile
\ No newline at end of file diff --git a/board/stm32l476g-eval/board.c b/board/stm32l476g-eval/board.c new file mode 100644 index 0000000000..37ff088090 --- /dev/null +++ b/board/stm32l476g-eval/board.c @@ -0,0 +1,20 @@ +/* Copyright 2016 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" +#include "gpio.h" +#include "hooks.h" +#include "registers.h" +#include "gpio_list.h" + +void tick_event(void) +{ + static int count; + + gpio_set_level(GPIO_LED_GREEN, (count & 0x03) == 0); + + count++; +} +DECLARE_HOOK(HOOK_TICK, tick_event, HOOK_PRIO_DEFAULT); diff --git a/board/stm32l476g-eval/board.h b/board/stm32l476g-eval/board.h new file mode 100644 index 0000000000..b4972a63cb --- /dev/null +++ b/board/stm32l476g-eval/board.h @@ -0,0 +1,42 @@ +/* Copyright 2016 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* STM32L476G-Eval board configuration */ + +#ifndef __CROS_EC_BOARD_H +#define __CROS_EC_BOARD_H + +/* Optional features */ +#undef CONFIG_WATCHDOG_HELP +#undef CONFIG_LID_SWITCH + +/* the UART console is on USART1 (PB6/7) */ +#undef CONFIG_UART_CONSOLE +#define CONFIG_UART_CONSOLE 1 + +/* Use USART1 for DMA TX */ +#define CONFIG_UART_TX_DMA_CH STM32_DMAC_USART1_TX +#define CONFIG_UART_TX_DMA_PH 2 + +/* Optional features */ +#define CONFIG_STM_HWTIMER32 + +/* + * Allow dangerous commands all the time, since we don't have a write protect + * switch. + */ +#define CONFIG_SYSTEM_UNLOCKED + +#ifndef __ASSEMBLER__ + +#undef CONFIG_FLASH + +/* Timer selection */ +#define TIM_CLOCK32 5 + +#include "gpio_signal.h" + +#endif /* !__ASSEMBLER__ */ +#endif /* __CROS_EC_BOARD_H */ diff --git a/board/stm32l476g-eval/build.mk b/board/stm32l476g-eval/build.mk new file mode 100644 index 0000000000..23c7cd9d38 --- /dev/null +++ b/board/stm32l476g-eval/build.mk @@ -0,0 +1,12 @@ +# -*- makefile -*- +# Copyright 2016 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Board specific files build + +CHIP:=stm32 +CHIP_FAMILY:=stm32l4 +CHIP_VARIANT:=stm32l476 + +board-y=board.o diff --git a/board/stm32l476g-eval/ec.tasklist b/board/stm32l476g-eval/ec.tasklist new file mode 100644 index 0000000000..0c19123e58 --- /dev/null +++ b/board/stm32l476g-eval/ec.tasklist @@ -0,0 +1,21 @@ +/* Copyright 2016 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/** + * List of enabled tasks in the priority order + * + * The first one has the lowest priority. + * + * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and + * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries, + * where : + * 'n' in the name of the task + * 'r' in the main routine of the task + * 'd' in an opaque parameter passed to the routine at startup + * 's' is the stack size in bytes; must be a multiple of 8 + */ +#define CONFIG_TASK_LIST \ + TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) diff --git a/board/stm32l476g-eval/gpio.inc b/board/stm32l476g-eval/gpio.inc new file mode 100644 index 0000000000..3028956ad4 --- /dev/null +++ b/board/stm32l476g-eval/gpio.inc @@ -0,0 +1,19 @@ +/* -*- mode:c -*- + * + * Copyright 2016 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Declare symbolic names for all the GPIOs that we care about. + * Note: Those with interrupt handlers must be declared first. */ + +/* Outputs */ +GPIO(LED_GREEN, PIN(B, 2), GPIO_OUT_LOW) +GPIO(LED_RED, PIN(C, 1), GPIO_OUT_LOW) + +/* Unimplemented signals which we need to emulate for now */ +UNIMPLEMENTED(ENTERING_RW) +UNIMPLEMENTED(WP_L) + +ALTERNATE(PIN_MASK(B, 0xC0), GPIO_ALT_F7, MODULE_UART, 0) /* USART1: PB6/7 */ diff --git a/board/stm32l476g-eval/openocd-flash.cfg b/board/stm32l476g-eval/openocd-flash.cfg new file mode 100644 index 0000000000..a347f88b79 --- /dev/null +++ b/board/stm32l476g-eval/openocd-flash.cfg @@ -0,0 +1,19 @@ +# Copyright 2016 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +source [find board/stm32l4discovery.cfg] + +# For flashing, force the board into reset on connect, this ensures that +# code running on the core can't interfere with programming. +reset_config connect_assert_srst + +gdb_port 0 +tcl_port 0 +telnet_port 0 +init +reset init +flash write_image erase $BUILD_DIR/ec.bin 0x08000000 +reset halt +resume +shutdown |