diff options
| author | Keith Short <keithshort@chromium.org> | 2019-10-29 14:57:19 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-11-01 04:36:49 +0000 |
| commit | 28b8d229927d285043fcdaf5043456cf20865a7e (patch) | |
| tree | dffeaa97ed96df6a32e4afbe6a21035768ce7c2f /board/tglrvpu_ite/gpio.inc | |
| parent | 7dece1affb2b8bcaa449743937c55774a0aa2ee0 (diff) | |
| download | chrome-ec-28b8d229927d285043fcdaf5043456cf20865a7e.tar.gz | |
tigerlake/icelake: add support for SYS_PWROK
Add code to pass through PG_EC_ALL_SYS_PWRGD from the platform to the
PCH signal PCH_SYS_PWROK.
These signals correspond to the Intel signal names ALL_SYS_PWRGD and
PCH_SYS_PWROK, respectively.
BUG=b:143373337
BRANCH=none
TEST=make buildall -j
Change-Id: Iff86508450a5bca8c97fb855fa1a3a586edd99ff
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881753
Commit-Queue: Sean Abraham <seanabraham@chromium.org>
Diffstat (limited to 'board/tglrvpu_ite/gpio.inc')
| -rw-r--r-- | board/tglrvpu_ite/gpio.inc | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/board/tglrvpu_ite/gpio.inc b/board/tglrvpu_ite/gpio.inc index d7acc76b92..d085647237 100644 --- a/board/tglrvpu_ite/gpio.inc +++ b/board/tglrvpu_ite/gpio.inc @@ -63,11 +63,25 @@ GPIO(SYS_RESET_L, PIN(B, 6), GPIO_ODR_HIGH) GPIO(PCH_RSMRST_L, PIN(C, 6), GPIO_OUT_LOW) GPIO(PCH_PWRBTN_L, PIN(D, 0), GPIO_ODR_HIGH) GPIO(EC_SPI_OE_N, PIN(I, 2), GPIO_OUT_LOW) -GPIO(PCH_SYS_PWROK, PIN(K, 4), GPIO_INPUT) /* Driven by Silego chip on RVP */ +/* + * PCH_SYS_PWROK is an input, driven by the Silego chip. The common x86 + * power sequencing expects that PCH_SYS_PWROK is an output and will drive + * this signal if GPIO_PCH_SYS_PWROK is configured. Map this pin as no-connect + * so that state can be monitored using the console. + */ +GPIO(NC_PCH_SYS_PWROK, PIN(K, 4), GPIO_INPUT) GPIO(EN_PP5000, PIN(L, 4), GPIO_OUT_LOW) GPIO(EN_PP3300_A, PIN(K, 2), GPIO_OUT_LOW) GPIO(EC_PCH_DSW_PWROK, PIN(L, 6), GPIO_OUT_LOW) +/* + * SYS_PWROK driven directly to AP by Silego, EC not needed for generation. + * PCH_SYS_PWROK is routed to EC, but mark unimplemented to prevent common + * Ice Lake code from driving signal. + */ +UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD) +UNIMPLEMENTED(PCH_SYS_PWROK) + /* Host communication GPIOs */ GPIO(PCH_WAKE_L, PIN(J, 0), GPIO_ODR_HIGH) #ifndef CONFIG_HOSTCMD_ESPI |