diff options
| author | Vijay Hiremath <vijay.p.hiremath@intel.com> | 2020-08-11 22:07:45 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-08-15 01:28:27 +0000 |
| commit | 29ad5a3e08fef053ffe8d56d004d868a8794481a (patch) | |
| tree | 173e52563c05388073bf889a847cf3ba93982534 /board/tglrvpu_ite | |
| parent | 16f541417ac84949c9b9e02152422e4131672e38 (diff) | |
| download | chrome-ec-29ad5a3e08fef053ffe8d56d004d868a8794481a.tar.gz | |
tglrvp: Enable early firmware selection EFS2
BUG=none
BRANCH=none
TEST=Software sync enabled Coreboot selects EC RW at early stage
Change-Id: Ib10a15b8e0b006ea830fe1b07725bf4e8ce4591f
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2351624
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'board/tglrvpu_ite')
| -rw-r--r-- | board/tglrvpu_ite/board.h | 4 | ||||
| -rw-r--r-- | board/tglrvpu_ite/gpio.inc | 5 |
2 files changed, 6 insertions, 3 deletions
diff --git a/board/tglrvpu_ite/board.h b/board/tglrvpu_ite/board.h index 6eddb96b9b..d6d238fdb9 100644 --- a/board/tglrvpu_ite/board.h +++ b/board/tglrvpu_ite/board.h @@ -21,6 +21,10 @@ /* Temperature sensor */ #define CONFIG_TEMP_SENSOR +/* Support early firmware selection */ +#define CONFIG_VBOOT_EFS2 +#define GPIO_PACKET_MODE_EN GPIO_ME_G3_TO_ME_EC + #include "baseboard.h" #define CONFIG_CHIPSET_TIGERLAKE diff --git a/board/tglrvpu_ite/gpio.inc b/board/tglrvpu_ite/gpio.inc index 9ce04cdc71..34235266e0 100644 --- a/board/tglrvpu_ite/gpio.inc +++ b/board/tglrvpu_ite/gpio.inc @@ -154,6 +154,8 @@ GPIO(FAN_POWER_EN, PIN(K, 6), GPIO_OUT_LOW) /* H1 pins */ GPIO(CCD_MODE_ODL, PIN(B, 5), GPIO_INPUT) GPIO(ENTERING_RW, PIN(C, 5), GPIO_OUT_LOW) +/* ME_GE_TO_ME_EC pin is re-purposed for H1 Packet Mode indication */ +GPIO(ME_G3_TO_ME_EC, PIN(H, 3), GPIO_OUT_LOW) /* Used with Discrete TBT and or with PD on RVP */ GPIO(NC_TBT_C0_RESET_N, PIN(KSO_H, 7), GPIO_INPUT) @@ -161,9 +163,6 @@ GPIO(NC_TBT_C1_RESET_N, PIN(K, 7), GPIO_INPUT) GPIO(NC_USB_C0_RETIMER_ALRT, PIN(I, 7), GPIO_INPUT) GPIO(NC_USB_C1_RETIMER_ALRT, PIN(G, 0), GPIO_INPUT) -/* Used if PMIC is used */ -GPIO(NC_PMIC_EN, PIN(H, 3), GPIO_INPUT) - /* Used if Base EC is present */ GPIO(NC_EC_BASE_DET, PIN(I, 3), GPIO_INPUT) |