diff options
| author | Vijay Hiremath <vijay.p.hiremath@intel.com> | 2019-09-04 15:59:45 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-09-05 23:04:33 +0000 |
| commit | df7ecbc55f4b7d67174a14db9dc781789f07ac60 (patch) | |
| tree | 1a96ae424a2a2400fc81b9d0b313f8ef435aa0e0 /board/tglrvpu_ite | |
| parent | b47a5ca84dfd6b75a4cd76837d81cac0345c000f (diff) | |
| download | chrome-ec-df7ecbc55f4b7d67174a14db9dc781789f07ac60.tar.gz | |
power: Add power sequencing logic for Tigerlake chipset
Power sequencing logic for Tigerlake is same as Icelake hence
reusing the Icelake code.
BUG=b:140508849
BRANCH=none
TEST=tglrvp can boot to S0
Change-Id: Id218422146e5549aa5b246ddbcaedd8e442e376b
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1785685
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'board/tglrvpu_ite')
| -rw-r--r-- | board/tglrvpu_ite/board.h | 5 | ||||
| -rw-r--r-- | board/tglrvpu_ite/gpio.inc | 2 |
2 files changed, 3 insertions, 4 deletions
diff --git a/board/tglrvpu_ite/board.h b/board/tglrvpu_ite/board.h index a844215e46..dc6b41035e 100644 --- a/board/tglrvpu_ite/board.h +++ b/board/tglrvpu_ite/board.h @@ -23,8 +23,9 @@ #include "baseboard.h" -/* TODO: Chipset Tigerlake */ -#define CONFIG_CHIPSET_ICELAKE +#define CONFIG_CHIPSET_TIGERLAKE +#define GPIO_EC_PCH_RSMRST_L GPIO_PCH_RSMRST_L +#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD /* Charger */ #define CONFIG_CHARGER_ISL9241 diff --git a/board/tglrvpu_ite/gpio.inc b/board/tglrvpu_ite/gpio.inc index 8622989e7f..4994154742 100644 --- a/board/tglrvpu_ite/gpio.inc +++ b/board/tglrvpu_ite/gpio.inc @@ -65,8 +65,6 @@ GPIO(PCH_SYS_PWROK, PIN(K, 4), GPIO_INPUT) /* Driven by Silego chip on RVP */ GPIO(EN_PP5000, PIN(L, 4), GPIO_OUT_LOW) GPIO(EN_PP3300_A, PIN(K, 2), GPIO_OUT_LOW) GPIO(EC_PCH_DSW_PWROK, PIN(L, 6), GPIO_OUT_LOW) -UNIMPLEMENTED(PG_EC_RSMRST_ODL) /* Not present on TGLRVP */ -UNIMPLEMENTED(EC_PCH_RSMRST_L) /* Not present on TGLRVP */ /* Host communication GPIOs */ GPIO(PCH_WAKE_L, PIN(J, 0), GPIO_ODR_HIGH) |