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authorGwendal Grignou <gwendal@chromium.org>2019-03-11 15:57:52 -0700
committerchrome-bot <chrome-bot@chromium.org>2019-03-26 04:42:55 -0700
commitbb266fc26fc05d4ab22de6ad7bce5b477c9f9140 (patch)
treef6ada087f62246c3a9547e649ac8846b0ed6d5ab /board/twinkie
parent0bfc511527cf2aebfa163c63a1d028419ca0b0c3 (diff)
downloadchrome-ec-bb266fc26fc05d4ab22de6ad7bce5b477c9f9140.tar.gz
common: replace 1 << digits, with BIT(digits)
Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'board/twinkie')
-rw-r--r--board/twinkie/board.c6
-rw-r--r--board/twinkie/simpletrace.c2
-rw-r--r--board/twinkie/sniffer.c4
-rw-r--r--board/twinkie/usb_pd_config.h6
4 files changed, 9 insertions, 9 deletions
diff --git a/board/twinkie/board.c b/board/twinkie/board.c
index 513d45d9a7..f15a55400c 100644
--- a/board/twinkie/board.c
+++ b/board/twinkie/board.c
@@ -34,10 +34,10 @@ void vbus_event(enum gpio_signal signal)
void board_config_pre_init(void)
{
/* enable SYSCFG clock */
- STM32_RCC_APB2ENR |= 1 << 0;
+ STM32_RCC_APB2ENR |= BIT(0);
/* Remap USART DMA to match the USART driver and TIM2 DMA */
- STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10) /* Remap USART1 RX/TX DMA */
- | (1 << 29);/* Remap TIM2 DMA */
+ STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10) /* Remap USART1 RX/TX DMA */
+ | BIT(29);/* Remap TIM2 DMA */
/* 40 MHz pin speed on UART PA9/PA10 */
STM32_GPIO_OSPEEDR(GPIO_A) |= 0x003C0000;
/* 40 MHz pin speed on TX clock out PB9 */
diff --git a/board/twinkie/simpletrace.c b/board/twinkie/simpletrace.c
index e2ee05daab..dc116d951a 100644
--- a/board/twinkie/simpletrace.c
+++ b/board/twinkie/simpletrace.c
@@ -223,7 +223,7 @@ void trace_packets(void)
dma_disable(STM32_DMAC_CH7);
task_disable_irq(STM32_IRQ_DMA_CHANNEL_4_7);
/* remove TIM1 CH1/2/3 DMA remapping */
- STM32_SYSCFG_CFGR1 &= ~(1 << 28);
+ STM32_SYSCFG_CFGR1 &= ~BIT(28);
#endif
/* "classical" PD RX configuration */
diff --git a/board/twinkie/sniffer.c b/board/twinkie/sniffer.c
index dbdcbb68a7..e35b457ff7 100644
--- a/board/twinkie/sniffer.c
+++ b/board/twinkie/sniffer.c
@@ -256,7 +256,7 @@ static void rx_timer_init(int tim_id, timer_ctlr_t *tim, int ch_idx, int up_idx)
void sniffer_init(void)
{
/* remap TIM1 CH1/2/3 to DMA channel 6 */
- STM32_SYSCFG_CFGR1 |= 1 << 28;
+ STM32_SYSCFG_CFGR1 |= BIT(28);
/* TIM1 CH1 for CC1 RX */
rx_timer_init(TIM_RX1, (void *)STM32_TIM_BASE(TIM_RX1),
@@ -266,7 +266,7 @@ void sniffer_init(void)
TIM_RX2_CCR_IDX, 2);
/* turn on COMP/SYSCFG */
- STM32_RCC_APB2ENR |= 1 << 0;
+ STM32_RCC_APB2ENR |= BIT(0);
STM32_COMP_CSR = STM32_COMP_CMP1EN | STM32_COMP_CMP1MODE_HSPEED |
STM32_COMP_CMP1INSEL_VREF12 |
STM32_COMP_CMP1OUTSEL_TIM1_IC1 |
diff --git a/board/twinkie/usb_pd_config.h b/board/twinkie/usb_pd_config.h
index b125a2dfa9..1b2c22ba1a 100644
--- a/board/twinkie/usb_pd_config.h
+++ b/board/twinkie/usb_pd_config.h
@@ -51,7 +51,7 @@ static inline void spi_enable_clock(int port)
#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
#define TIM_CCR_CS 1
-#define EXTI_COMP_MASK(p) ((1 << 21) | (1 << 22))
+#define EXTI_COMP_MASK(p) (BIT(21) | BIT(22))
#define IRQ_COMP STM32_IRQ_COMP
/* triggers packet detection on comparator falling edge */
#define EXTI_XTSR STM32_EXTI_FTSR
@@ -71,8 +71,8 @@ static inline void pd_set_pins_speed(int port)
static inline void pd_tx_spi_reset(int port)
{
/* Reset SPI1 */
- STM32_RCC_APB2RSTR |= (1 << 12);
- STM32_RCC_APB2RSTR &= ~(1 << 12);
+ STM32_RCC_APB2RSTR |= BIT(12);
+ STM32_RCC_APB2RSTR &= ~BIT(12);
}
/* Drive the CC line from the TX block */