diff options
author | Vincent Palatin <vpalatin@chromium.org> | 2021-01-25 11:49:10 +0100 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2021-02-01 11:30:23 +0000 |
commit | f588101b7a8c41e8eefa321fe1ba123fbfe19449 (patch) | |
tree | f76839942cda08d72587563dca3269f6fcfa7e92 /board/vilboz | |
parent | b7043cbd98fc5889bfbd6ef607f95334cb827c08 (diff) | |
download | chrome-ec-f588101b7a8c41e8eefa321fe1ba123fbfe19449.tar.gz |
vilboz: enable USB 3 mux for the LTE modem
On Vilboz360, if an internal LTE modem is present, it is connected on
the USB C1 port. In this case we need to ensure that the superspeed mux
of the C1 port is in USB 3 position rather than in 'safe mode' where the
LTE modem would enumerate only as USB 2.0 HS since the superspeed pairs
would be disconnected.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=b:177389383
BRANCH=zork
TEST=On vilboz360, see the L850-gl LTE modem enumerating as a superspeed
device.
Change-Id: I0f3e100077552a8712b2177b3a066e124e149dab
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2645429
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'board/vilboz')
-rw-r--r-- | board/vilboz/board.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/board/vilboz/board.c b/board/vilboz/board.c index 0a2a4536ea..af97c5b211 100644 --- a/board/vilboz/board.c +++ b/board/vilboz/board.c @@ -413,6 +413,25 @@ static void setup_fw_config(void) } DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2); +static void lte_usb3_mux_init(void) +{ + /* + * the USB_C1 port might be used for the LTE modem if it is not used + * for type-C, we need to keep the superspeed mux in USB 3 position. + */ + if (ec_config_lte_present() == LTE_PRESENT) { + const struct usb_mux usb_c1 = { + .usb_port = 1 /* USBC_PORT_C1 */, + .i2c_port = I2C_PORT_USB_AP_MUX, + .i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS, + .driver = &amd_fp5_usb_mux_driver, + }; + /* steer the mux to connect the USB 3 superspeed pairs */ + usb_c1.driver->set(&usb_c1, USB_PD_MUX_USB_ENABLED); + } +} +DECLARE_HOOK(HOOK_CHIPSET_RESUME, lte_usb3_mux_init, HOOK_PRIO_DEFAULT); + static void lte_function_resume(void) { gpio_set_level(GPIO_LTE_FCPO, 1); |