diff options
author | Aseda Aboagye <aaboagye@google.com> | 2022-01-10 17:26:56 -0600 |
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committer | Aseda Aboagye <aaboagye@google.com> | 2022-01-10 17:26:56 -0600 |
commit | dc11829e169a9c425860ec5cca949ef80df9e0b7 (patch) | |
tree | 0517b0831c6e52b347926a1b727741df380e908c /board/volmar/usbc_config.c | |
parent | c5bd23a4b204565dab616f7fa4ee8a0b7b433d4c (diff) | |
parent | b44d10f8f79cadb259cc7ab79714a0919fc0c4c8 (diff) | |
download | chrome-ec-firmware-keeby-14119.B-main.tar.gz |
Merge remote-tracking branch cros/main into firmware-keeby-14119.B-mainfirmware-keeby-14119.B-main
Relevant changes:
git log --oneline c5bd23a4b..b44d10f8f -- baseboard/dedede board/cappy2
board/corori board/driblee board/gooey board/haboki board/lalala
board/waddledoo2 common/charge_state_v2.c common/mkbp_* common/ocpc.c
common/usbc/usb_tc_drp_acc_trysrc_sm.c common/usbc/usb_sm.c
common/usbc/*_pd_* common/usbc/dp_alt_mode.c common/usbc/usb_prl_sm.c
common/usbc/usb_pe_drp_sm.c common/usb_charger.c common/usb_common.c
common/usbc_ocp.c driver/charger/sm5803.* driver/charger/isl923x.*
driver/tcpm/raa489000.* driver/tcpm/it83* include/power/icelake.h
include/intel_x86.h power/icelake.c power/intel_x86.c util/getversion.sh
42d03a001 config: change temp_sensor_power from config to gpio
e296efb28 usb_common: Fix CONFIG_USB_PD_DISCHARGE_TCPC typo
c346481f4 atomic: cast to unsigned when shifting
9b972a0f2 driver/tcpm/it83xx, it8xxx2: ITE inactive port return from HOOK
a499d8fd4 driver/tcpm/it83xx, it8xxx2: set sleep mask for mixed TCPC case
ed62e2583 TCPMv2: don't set the sleep mask for TCPC embedded in EC
c962696e8 motion_sensor: Remove |int_signal| field
86b216794 ocpc: modify pre-charge target condition
6f8336eb4 dedede: Set MKBP event wake mask to 0
02d034df0 dedede: add stylus fw_config
4f7cd7509 atomic: use atomic_t where it is possible
e3ffa0519 mkbp: change the type fifo_entries to atomic_t
bb4c47af0 usb: use atomic_t where possible
c6e513ee2 power/icelake: Add SLP_S5 as a watched power signal
d89e49b20 power: Introduce S4 as a real power state
ba8a3c9c0 chgstv2: Use chipset_in_state instead of naming states
23a975d12 i2c: Use declared initializers for i2c_ports: boards a-l
35865dbec TCPMv2: Guard DATA_RESET using CONFIG_USB_PD_DATA_RESET_MSG
d4d8243ed i2c: Use declared initializers for i2c_ports: baseboards
eba8d0305 RAA489000: Fixed RAA489000 max charging current
e78b83e0f TCPMv2: Delay Data Reset until mode entry request
6230e60fc TCPMv2: Support Data Reset as DFP, initiator
412246836 intel_x86: Apply chipset resume init and suspend complete hooks
f2809b72c config: rename CONFIG_HOSTCMD_ESPI to CONFIG_HOST_INTERFACE_ESPI
BRANCH=None
BUG=b:202796060 b:207805856 b:167983049 b:208318528 b:181983966
BUG=b:207328258 b:195416058 b:205285137 b:199919093 b:207055975
BUG=b:129159505 b:204947672 b:141363146 b:207082842 b:205675485
TEST=`make -j buildall`
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: I980351977e11088a130e478df0701be4715f049b
Diffstat (limited to 'board/volmar/usbc_config.c')
-rw-r--r-- | board/volmar/usbc_config.c | 506 |
1 files changed, 506 insertions, 0 deletions
diff --git a/board/volmar/usbc_config.c b/board/volmar/usbc_config.c new file mode 100644 index 0000000000..e1d899f7fc --- /dev/null +++ b/board/volmar/usbc_config.c @@ -0,0 +1,506 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <stdint.h> +#include <stdbool.h> + +#include "cbi.h" +#include "charger.h" +#include "charge_ramp.h" +#include "common.h" +#include "compile_time_macros.h" +#include "console.h" +#include "driver/bc12/pi3usb9201_public.h" +#include "driver/ppc/nx20p348x.h" +#include "driver/ppc/syv682x_public.h" +#include "driver/retimer/bb_retimer_public.h" +#include "driver/tcpm/nct38xx.h" +#include "driver/tcpm/ps8xxx_public.h" +#include "driver/tcpm/tcpci.h" +#include "ec_commands.h" +#include "fw_config.h" +#include "gpio.h" +#include "gpio_signal.h" +#include "hooks.h" +#include "ioexpander.h" +#include "system.h" +#include "task.h" +#include "task_id.h" +#include "timer.h" +#include "usbc_config.h" +#include "usbc_ppc.h" +#include "usb_charge.h" +#include "usb_mux.h" +#include "usb_pd.h" +#include "usb_pd_tcpm.h" + +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) + +/* USBC TCPC configuration */ +const struct tcpc_config_t tcpc_config[] = { + [USBC_PORT_C0] = { + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C0_C2_TCPC, + .addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS, + }, + .drv = &nct38xx_tcpm_drv, + .flags = TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_NO_DEBUG_ACC_CONTROL, + }, + [USBC_PORT_C1] = { + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C1_TCPC, + .addr_flags = PS8751_I2C_ADDR1_FLAGS, + }, + .drv = &ps8xxx_tcpm_drv, + .flags = TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V | + TCPC_FLAGS_CONTROL_VCONN, + }, + [USBC_PORT_C2] = { + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C0_C2_TCPC, + .addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS, + }, + .drv = &nct38xx_tcpm_drv, + .flags = TCPC_FLAGS_TCPCI_REV2_0, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT); +BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT); + +/******************************************************************************/ +/* USB-A charging control */ + +const int usb_port_enable[USB_PORT_COUNT] = { + GPIO_EN_PP5000_USBA_R, +}; +BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT); + +/******************************************************************************/ + +/* USBC PPC configuration */ +struct ppc_config_t ppc_chips[] = { + [USBC_PORT_C0] = { + .i2c_port = I2C_PORT_USB_C0_C2_PPC, + .i2c_addr_flags = SYV682X_ADDR0_FLAGS, + .drv = &syv682x_drv, + }, + [USBC_PORT_C1] = { + /* Compatible with Silicon Mitus SM536A0 */ + .i2c_port = I2C_PORT_USB_C1_PPC, + .i2c_addr_flags = NX20P3483_ADDR2_FLAGS, + .drv = &nx20p348x_drv, + }, + [USBC_PORT_C2] = { + .i2c_port = I2C_PORT_USB_C0_C2_PPC, + /* + * b/179987870 + * schematics I2C map says ADDR3 + */ + .i2c_addr_flags = SYV682X_ADDR2_FLAGS, + .drv = &syv682x_drv, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT); + +unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); + +/* USBC mux configuration - Alder Lake includes internal mux */ +static const struct usb_mux usbc0_tcss_usb_mux = { + .usb_port = USBC_PORT_C0, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, +}; +static const struct usb_mux usbc2_tcss_usb_mux = { + .usb_port = USBC_PORT_C2, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, +}; + +/* + * USB3 DB mux configuration - the top level mux still needs to be set + * to the virtual_usb_mux_driver so the AP gets notified of mux changes + * and updates the TCSS configuration on state changes. + */ +static const struct usb_mux usbc1_usb3_db_retimer = { + .usb_port = USBC_PORT_C1, + .driver = &tcpci_tcpm_usb_mux_driver, + .hpd_update = &ps8xxx_tcpc_update_hpd_status, +}; + +const struct usb_mux usb_muxes[] = { + [USBC_PORT_C0] = { + .usb_port = USBC_PORT_C0, + .driver = &bb_usb_retimer, + .hpd_update = bb_retimer_hpd_update, + .i2c_port = I2C_PORT_USB_C0_C2_MUX, + .i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR, + .next_mux = &usbc0_tcss_usb_mux, + }, + [USBC_PORT_C1] = { + /* PS8815 DB */ + .usb_port = USBC_PORT_C1, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, + .next_mux = &usbc1_usb3_db_retimer, + }, + [USBC_PORT_C2] = { + .usb_port = USBC_PORT_C2, + .driver = &bb_usb_retimer, + .hpd_update = bb_retimer_hpd_update, + .i2c_port = I2C_PORT_USB_C0_C2_MUX, + .i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR, + .next_mux = &usbc2_tcss_usb_mux, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT); + +/* BC1.2 charger detect configuration */ +const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = { + [USBC_PORT_C0] = { + .i2c_port = I2C_PORT_USB_C0_C2_BC12, + .i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS, + }, + [USBC_PORT_C1] = { + .i2c_port = I2C_PORT_USB_C1_BC12, + .i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS, + }, + [USBC_PORT_C2] = { + .i2c_port = I2C_PORT_USB_C0_C2_BC12, + .i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT); + +/* + * USB C0 and C2 uses burnside bridge chips and have their reset + * controlled by their respective TCPC chips acting as GPIO expanders. + * + * ioex_init() is normally called before we take the TCPCs out of + * reset, so we need to start in disabled mode, then explicitly + * call ioex_init(). + */ + +struct ioexpander_config_t ioex_config[] = { + [IOEX_C0_NCT38XX] = { + .i2c_host_port = I2C_PORT_USB_C0_C2_TCPC, + .i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS, + .drv = &nct38xx_ioexpander_drv, + .flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED, + }, + [IOEX_C2_NCT38XX] = { + .i2c_host_port = I2C_PORT_USB_C0_C2_TCPC, + .i2c_addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS, + .drv = &nct38xx_ioexpander_drv, + .flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED, + }, + [IOEX_ID_1_C0_NCT38XX] = { + .i2c_host_port = I2C_PORT_USB_C0_C2_TCPC, + .i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS, + .drv = &nct38xx_ioexpander_drv, + .flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED, + }, + [IOEX_ID_1_C2_NCT38XX] = { + .i2c_host_port = I2C_PORT_USB_C0_C2_TCPC, + .i2c_addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS, + .drv = &nct38xx_ioexpander_drv, + .flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT); + +#ifdef CONFIG_CHARGE_RAMP_SW + +/* + * TODO(b/181508008): tune this threshold + */ + +#define BC12_MIN_VOLTAGE 4400 + +/** + * Return true if VBUS is too low + */ +int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) +{ + int voltage; + + if (charger_get_vbus_voltage(port, &voltage)) + voltage = 0; + + if (voltage == 0) { + CPRINTS("%s: must be disconnected", __func__); + return 1; + } + + if (voltage < BC12_MIN_VOLTAGE) { + CPRINTS("%s: port %d: vbus %d lower than %d", __func__, + port, voltage, BC12_MIN_VOLTAGE); + return 1; + } + + return 0; +} + +#endif /* CONFIG_CHARGE_RAMP_SW */ + +void config_usb_db_type(void) +{ + enum ec_cfg_usb_db_type db_type = ec_cfg_usb_db_type(); + + /* + * TODO(b/180434685): implement multiple DB types + */ + + CPRINTS("Configured USB DB type number is %d", db_type); +} + +__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable) +{ + enum ioex_signal rst_signal; + + if (me->usb_port == USBC_PORT_C0) { + if (get_board_id() == 1) + rst_signal = IOEX_ID_1_USB_C0_RT_RST_ODL; + else + rst_signal = IOEX_USB_C0_RT_RST_ODL; + } else if (me->usb_port == USBC_PORT_C2) { + if (get_board_id() == 1) + rst_signal = IOEX_ID_1_USB_C2_RT_RST_ODL; + else + rst_signal = IOEX_USB_C2_RT_RST_ODL; + } else { + return EC_ERROR_INVAL; + } + + /* + * We do not have a load switch for the burnside bridge chips, + * so we only need to sequence reset. + */ + + if (enable) { + /* + * Tpw, minimum time from VCC to RESET_N de-assertion is 100us. + * For boards that don't provide a load switch control, the + * retimer_init() function ensures power is up before calling + * this function. + */ + ioex_set_level(rst_signal, 1); + /* + * Allow 1ms time for the retimer to power up lc_domain + * which powers I2C controller within retimer + */ + msleep(1); + if (get_board_id() == 1) { + int val; + + /* + * Check if we were able to deassert + * reset. Board ID 1 uses a GPIO that is + * uncontrollable when a debug accessory is + * connected. + */ + if (ioex_get_level(rst_signal, &val) != EC_SUCCESS) + return EC_ERROR_UNKNOWN; + if (val != 1) + return EC_ERROR_NOT_POWERED; + } + } else { + ioex_set_level(rst_signal, 0); + msleep(1); + } + return EC_SUCCESS; +} + +void board_reset_pd_mcu(void) +{ + enum gpio_signal tcpc_rst; + + if (get_board_id() == 1) + tcpc_rst = GPIO_ID_1_USB_C0_C2_TCPC_RST_ODL; + else + tcpc_rst = GPIO_USB_C0_C2_TCPC_RST_ODL; + + /* + * TODO(b/179648104): figure out correct timing + */ + + gpio_set_level(tcpc_rst, 0); + if (ec_cfg_usb_db_type() != DB_USB_ABSENT) { + gpio_set_level(GPIO_USB_C1_RST_ODL, 0); + gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 0); + } + + /* + * delay for power-on to reset-off and min. assertion time + */ + + msleep(20); + + gpio_set_level(tcpc_rst, 1); + if (ec_cfg_usb_db_type() != DB_USB_ABSENT) { + gpio_set_level(GPIO_USB_C1_RST_ODL, 1); + gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1); + } + + /* wait for chips to come up */ + + msleep(50); +} + +static void board_tcpc_init(void) +{ + /* Don't reset TCPCs after initial reset */ + if (!system_jumped_late()) + board_reset_pd_mcu(); + + /* + * These IO expander pins are implemented using the + * C0/C2 TCPC, so they must be set up after the TCPC has + * been taken out of reset. + */ + if (get_board_id() == 1) { + ioex_init(IOEX_ID_1_C0_NCT38XX); + ioex_init(IOEX_ID_1_C2_NCT38XX); + } else { + ioex_init(IOEX_C0_NCT38XX); + ioex_init(IOEX_C2_NCT38XX); + } + + /* Enable PPC interrupts. */ + gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL); + gpio_enable_interrupt(GPIO_USB_C2_PPC_INT_ODL); + + /* Enable TCPC interrupts. */ + gpio_enable_interrupt(GPIO_USB_C0_C2_TCPC_INT_ODL); + + /* Enable BC1.2 interrupts. */ + gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL); + gpio_enable_interrupt(GPIO_USB_C2_BC12_INT_ODL); + + if (ec_cfg_usb_db_type() != DB_USB_ABSENT) { + gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL); + gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL); + gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL); + } +} +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET); + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + + if (gpio_get_level(GPIO_USB_C0_C2_TCPC_INT_ODL) == 0) + status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_2; + + if ((ec_cfg_usb_db_type() != DB_USB_ABSENT) && + gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0) + status |= PD_STATUS_TCPC_ALERT_1; + + return status; +} + +int ppc_get_alert_status(int port) +{ + if (port == USBC_PORT_C0) + return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0; + else if ((port == USBC_PORT_C1) && + (ec_cfg_usb_db_type() != DB_USB_ABSENT)) + return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0; + else if (port == USBC_PORT_C2) + return gpio_get_level(GPIO_USB_C2_PPC_INT_ODL) == 0; + return 0; +} + +void tcpc_alert_event(enum gpio_signal signal) +{ + switch (signal) { + case GPIO_USB_C0_C2_TCPC_INT_ODL: + schedule_deferred_pd_interrupt(USBC_PORT_C0); + break; + case GPIO_USB_C1_TCPC_INT_ODL: + if (ec_cfg_usb_db_type() == DB_USB_ABSENT) + break; + schedule_deferred_pd_interrupt(USBC_PORT_C1); + break; + default: + break; + } +} + +void bc12_interrupt(enum gpio_signal signal) +{ + switch (signal) { + case GPIO_USB_C0_BC12_INT_ODL: + task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12); + break; + case GPIO_USB_C1_BC12_INT_ODL: + if (ec_cfg_usb_db_type() == DB_USB_ABSENT) + break; + task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12); + break; + case GPIO_USB_C2_BC12_INT_ODL: + task_set_event(TASK_ID_USB_CHG_P2, USB_CHG_EVENT_BC12); + break; + default: + break; + } +} + +void ppc_interrupt(enum gpio_signal signal) +{ + switch (signal) { + case GPIO_USB_C0_PPC_INT_ODL: + syv682x_interrupt(USBC_PORT_C0); + break; + case GPIO_USB_C1_PPC_INT_ODL: + switch (ec_cfg_usb_db_type()) { + case DB_USB_ABSENT: + case DB_USB_ABSENT2: + break; + case DB_USB3_PS8815: + nx20p348x_interrupt(USBC_PORT_C1); + break; + } + break; + case GPIO_USB_C2_PPC_INT_ODL: + syv682x_interrupt(USBC_PORT_C2); + break; + default: + break; + } +} + +void retimer_interrupt(enum gpio_signal signal) +{ + /* + * TODO(b/179513527): add USB-C support + */ +} + +__override bool board_is_dts_port(int port) +{ + return port == USBC_PORT_C0; +} + +__override bool board_is_tbt_usb4_port(int port) +{ + if (port == USBC_PORT_C0 || port == USBC_PORT_C2) + return true; + + return false; +} + +__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port) +{ + if (!board_is_tbt_usb4_port(port)) + return TBT_SS_RES_0; + + return TBT_SS_TBT_GEN3; +} |