diff options
| author | Keith Short <keithshort@chromium.org> | 2019-10-29 14:57:19 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-11-01 04:36:49 +0000 |
| commit | 28b8d229927d285043fcdaf5043456cf20865a7e (patch) | |
| tree | dffeaa97ed96df6a32e4afbe6a21035768ce7c2f /board/volteer/gpio.inc | |
| parent | 7dece1affb2b8bcaa449743937c55774a0aa2ee0 (diff) | |
| download | chrome-ec-28b8d229927d285043fcdaf5043456cf20865a7e.tar.gz | |
tigerlake/icelake: add support for SYS_PWROK
Add code to pass through PG_EC_ALL_SYS_PWRGD from the platform to the
PCH signal PCH_SYS_PWROK.
These signals correspond to the Intel signal names ALL_SYS_PWRGD and
PCH_SYS_PWROK, respectively.
BUG=b:143373337
BRANCH=none
TEST=make buildall -j
Change-Id: Iff86508450a5bca8c97fb855fa1a3a586edd99ff
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881753
Commit-Queue: Sean Abraham <seanabraham@chromium.org>
Diffstat (limited to 'board/volteer/gpio.inc')
| -rw-r--r-- | board/volteer/gpio.inc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/board/volteer/gpio.inc b/board/volteer/gpio.inc index fee9e6f0c6..7f59cc0ab5 100644 --- a/board/volteer/gpio.inc +++ b/board/volteer/gpio.inc @@ -22,6 +22,7 @@ GPIO_INT(SLP_S3_L, PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(SLP_SUS_L, PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(PG_EC_RSMRST_ODL, PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(DSW_PWROK, PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(PG_EC_ALL_SYS_PWRGD, PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt) /* Sensor Interrupts */ @@ -50,7 +51,7 @@ GPIO(EC_RST_ODL, PIN(0, 2), GPIO_INT_BOTH | GPIO_LOCKED) /* AP/PCH Signals */ -GPIO(EC_PCH_SYS_PWROK, PIN(3, 7), GPIO_OUT_LOW) /* TODO - b/140556273 - implement support with power sequencing */ +GPIO(EC_PCH_SYS_PWROK, PIN(3, 7), GPIO_OUT_LOW) GPIO(EC_PCH_RSMRST_ODL, PIN(A, 6), GPIO_ODR_HIGH) /* TODO - b/140950085 - implement TGL sequencing requirement */ GPIO(EC_PCH_PWR_BTN_ODL, PIN(C, 1), GPIO_ODR_HIGH) GPIO(EC_PCH_RTCRST, PIN(7, 6), GPIO_OUT_LOW) |