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| author | Ben Chen <ben.chen2@quanta.corp-partner.google.com> | 2020-07-02 16:47:58 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-07-07 05:57:11 +0000 |
| commit | 94ff39b6e02e00882aeea8d2f5e1a417ffe00262 (patch) | |
| tree | 0867769bf8d65768d761673d15bc2150a4e4b57c /board/voxel/gpio.inc | |
| parent | b4db0c490e66368b3a2cb5bec9e4fd17c028589a (diff) | |
| download | chrome-ec-94ff39b6e02e00882aeea8d2f5e1a417ffe00262.tar.gz | |
voxel: supports bb_retimer for C0/C1 port
add bb retimer for C0/C1 port
BUG=b:155062762, b:155062762
BRANCH=none
TEST=make buildall PASS
Change-Id: I1da93b58eae4c28a8f7a7192518a130f80b848d9
Signed-off-by: Ben Chen <ben.chen2@quanta.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2275516
Reviewed-by: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'board/voxel/gpio.inc')
| -rw-r--r-- | board/voxel/gpio.inc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/board/voxel/gpio.inc b/board/voxel/gpio.inc index 7d31115492..bf142cd6b9 100644 --- a/board/voxel/gpio.inc +++ b/board/voxel/gpio.inc @@ -101,14 +101,16 @@ GPIO(EC_PCH_INT_ODL, PIN(B, 0), GPIO_ODR_HIGH) * so it's safe to define GPIOs compatible with both designs. * TODO (b/149858568): remove board ID=0 support. */ -GPIO(USB_C1_RT_RST_ODL_BOARDID_0, PIN(3, 2), GPIO_ODR_LOW) /* USB_C1 Reset on boards without board ID */ +GPIO(USB_C0_RT_RST_ODL, PIN(4, 1), GPIO_ODR_LOW) GPIO(USB_C1_RT_RST_ODL, PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset on boards board ID >=1 */ GPIO(USB_C0_OC_ODL, PIN(B, 1), GPIO_ODR_HIGH) GPIO(USB_C1_OC_ODL, PIN(5, 0), GPIO_ODR_HIGH) /* Don't have a load switch for retimer */ +UNIMPLEMENTED(USB_C0_LS_EN) UNIMPLEMENTED(USB_C1_LS_EN) /* Retimer Force Power enable is connected to AP */ +UNIMPLEMENTED(USB_C0_RT_FORCE_PWR) UNIMPLEMENTED(USB_C1_RT_FORCE_PWR) /* Misc Signals */ @@ -131,6 +133,8 @@ GPIO(EC_I2C2_USB_C1_SCL, PIN(9, 2), GPIO_INPUT) GPIO(EC_I2C2_USB_C1_SDA, PIN(9, 1), GPIO_INPUT) GPIO(EC_I2C3_USB_1_MIX_SCL, PIN(D, 1), GPIO_INPUT) GPIO(EC_I2C3_USB_1_MIX_SDA, PIN(D, 0), GPIO_INPUT) +GPIO(EC_I2C4_USB_1_MIX_SCL, PIN(F, 3), GPIO_INPUT) +GPIO(EC_I2C4_USB_1_MIX_SDA, PIN(F, 2), GPIO_INPUT) GPIO(EC_I2C5_POWER_SCL, PIN(3, 3), GPIO_INPUT) GPIO(EC_I2C5_POWER_SDA, PIN(3, 6), GPIO_INPUT) GPIO(EC_I2C7_EEPROM_SCL, PIN(B, 3), GPIO_INPUT) |