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authorBen Chen <ben.chen2@quanta.corp-partner.google.com>2020-09-01 11:13:18 +0800
committerCommit Bot <commit-bot@chromium.org>2020-09-02 04:43:40 +0000
commita387df008154ccdde0eac036f6760f5c36174348 (patch)
tree421002c1da4fc560fce006a6fedded2071a928cb /board/voxel
parentf2d1c7aca5aa87b3cfbd76fcc6db586bae9508d9 (diff)
downloadchrome-ec-a387df008154ccdde0eac036f6760f5c36174348.tar.gz
voxel:: modify mb gpio pin for BB retimer INT.
Add USB_C0_RT_INT_ODL/USB_C1_RT_INT_ODL default INPUT dtype for mb typec C0/C1 port. BUG=b:166003345 BRANCH=master TEST=make buildall PASS, check system can power on. Change-Id: Ibeb457d127b22d6d7c93481536cea864a7750dd9 Signed-off-by: Ben Chen <ben.chen2@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2386684 Reviewed-by: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'board/voxel')
-rw-r--r--board/voxel/gpio.inc4
1 files changed, 2 insertions, 2 deletions
diff --git a/board/voxel/gpio.inc b/board/voxel/gpio.inc
index 649ceef053..fafa5f5a47 100644
--- a/board/voxel/gpio.inc
+++ b/board/voxel/gpio.inc
@@ -97,6 +97,8 @@ GPIO(USB_C0_RT_RST_ODL, PIN(4, 1), GPIO_ODR_LOW)
GPIO(USB_C1_RT_RST_ODL, PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset on boards board ID >=1 */
GPIO(USB_C0_OC_ODL, PIN(B, 1), GPIO_ODR_HIGH)
GPIO(USB_C1_OC_ODL, PIN(5, 0), GPIO_ODR_HIGH)
+GPIO(USB_C0_RT_INT_ODL, PIN(C, 6), GPIO_INPUT)
+GPIO(USB_C1_RT_INT_ODL, PIN(9, 6), GPIO_INPUT)
/* Don't have a load switch for retimer */
UNIMPLEMENTED(USB_C0_LS_EN)
@@ -114,10 +116,8 @@ GPIO(EC_SLP_S0IX, PIN(7, 2), GPIO_INPUT | GPIO_PULL_UP)
/* Unused signals */
GPIO(UNUSED_GPIO34, PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO96, PIN(9, 6), GPIO_INPUT | GPIO_PULL_UP)
GPIO(UNUSED_GPIOA7, PIN(A, 7), GPIO_INPUT | GPIO_PULL_UP)
GPIO(UNUSED_GPIOC0, PIN(C, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOC6, PIN(C, 6), GPIO_INPUT | GPIO_PULL_UP)
/*
* eDP backlight - both PCH and EC have enable pins that must be high