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| author | Aseda Aboagye <aaboagye@google.com> | 2020-04-08 20:01:04 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-04-21 19:45:33 +0000 |
| commit | d8d1f71a4f5e53d97ab99f86a2cbd2aa1dd7a268 (patch) | |
| tree | 0dd7f28ccb6704ee9790e0b0a3793e50caf05c15 /board/waddledee/gpio.inc | |
| parent | 071e1b8f7604d2bcc3fe9d775b7d6098bf38dc50 (diff) | |
| download | chrome-ec-d8d1f71a4f5e53d97ab99f86a2cbd2aa1dd7a268.tar.gz | |
waddledoo/waddledee: Deassert ALL_SYS_PGOOD quickly
According to tPLT17 in the PDG, the time from SLP_S3_L assertion to
VCCIN_EN de-assertion should be less than 200us, but this was not
occurring on waddledoo. This commit adds a special interrupt handler
in order to meet that timing requirement by immediately deasserting
ALL_SYS_PGOOD once SLP_S3_L is asserted.
BUG=b:152552074
BRANCH=None
TEST=Build and flash waddledoo, boot and shut AP down, verify that the
time between SLP_S3_L asserting and ALL_SYS_PGOOD deasserting is less
than 200us.
TEST=`make -j buildall`
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: Ib34016d5bdfa956f410dde3e3b3074bd306a18f9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2142744
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'board/waddledee/gpio.inc')
| -rw-r--r-- | board/waddledee/gpio.inc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/board/waddledee/gpio.inc b/board/waddledee/gpio.inc index 7e36810de8..1d6838729a 100644 --- a/board/waddledee/gpio.inc +++ b/board/waddledee/gpio.inc @@ -10,16 +10,16 @@ /* Power State interrupts */ GPIO_INT(SLP_S4_L, PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt) -GPIO_INT(SLP_S3_L, PIN(H, 3), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(SLP_S3_L, PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt) GPIO_INT(SLP_S0_L, PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(SLP_SUS_L, PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(VCCIN_AUX_VID0, PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(RSMRST_PWRGD_L, PIN(E, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_signal_interrupt) GPIO_INT(CPU_C10_GATE_L, PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt) -GPIO_INT(PG_DRAM_OD, PIN(D, 3), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(PG_DRAM_OD, PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt) GPIO_INT(PG_PP1050_ST_OD, PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(VCCIN_AUX_VID1, PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt) -GPIO_INT(PG_VCCIO_EXT_OD, PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(PG_VCCIO_EXT_OD, PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt) GPIO_INT(ESPI_RESET_L, PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt) GPIO_INT(H1_EC_PWR_BTN_ODL, PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt) |