diff options
| author | Mulin Chao <mlchao@nuvoton.com> | 2016-08-04 14:20:36 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-08-12 05:24:34 -0700 |
| commit | 0558a242bbfbf4a2a1fec3c85c01767e30dee8f5 (patch) | |
| tree | 231b31c2e2d3e7625bbe7f12dc456a4b4c7debf9 /board/wheatley/gpio.inc | |
| parent | 2e738c72fd3676ef5e3b8ffcf51ad3fa488fe865 (diff) | |
| download | chrome-ec-0558a242bbfbf4a2a1fec3c85c01767e30dee8f5.tar.gz | |
wheatley: Modified board level drivers for eSPI POC on wheatley.
Modified board level drivers for eSPI POC on wheatley. By adding CONFIG_ESPI
definition, ec can support espi protocols for host interface on x86 based
platform such as skylake and so on. CONFIG_VW_SIGNALS will be used in the
future for saving GPIOs during power sequence.
Modified sources:
1. wheatley/board.h: Enable/disable espi driver.
2, wheatley/board.c: Add VW signals in power signal list.
3. wheatley/gpio.inc: Save GPIOs if CONFIG_VW_SIGNALS is defined.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make BOARD=wheatley; test nuvoton IC specific drivers
Change-Id: I0e8a951de6eacd4f8be65ffaac242f38079375d5
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/366520
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'board/wheatley/gpio.inc')
| -rw-r--r-- | board/wheatley/gpio.inc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/board/wheatley/gpio.inc b/board/wheatley/gpio.inc index 8d16b9d817..c50b184482 100644 --- a/board/wheatley/gpio.inc +++ b/board/wheatley/gpio.inc @@ -15,8 +15,11 @@ GPIO_INT(WP_L, PIN(7, 1), GPIO_INT_BOTH, switch GPIO_INT(POWER_BUTTON_L, PIN(9, 7), GPIO_INT_BOTH, power_button_interrupt) /* A48 - GPIO97 for ROP_EC_PWR_BTN_L_R */ /* RSMRST from PMIC */ GPIO_INT(RSMRST_L_PGOOD, PIN(7, 2), GPIO_INT_BOTH, power_signal_interrupt) /* A36 - PWRGD for ROP_EC_RSMRST_L */ +/* Use VW signals instead of GPIOs */ +#ifndef CONFIG_VW_SIGNALS GPIO_INT(PCH_SLP_S4_L, PIN(5, 0), GPIO_INT_BOTH, power_signal_interrupt) /* A25 - GPIO50 for SLP_S4_L */ GPIO_INT(PCH_SLP_S3_L, PIN(4, 0), GPIO_INT_BOTH, power_signal_interrupt) /* B21 - TA1 for SLP_S3_L */ +#endif /* * This pulldown should be removed in future hardware followers. The signal * is pulled up in the SoC when the primary rails are on and/or ramping. |