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authorJagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>2018-05-15 15:00:42 -0700
committerchrome-bot <chrome-bot@chromium.org>2018-05-22 15:54:11 -0700
commit2c9c55da93f57ac8eaef47328239d8957fd4a5d6 (patch)
tree348f0db9253c9e8e5a09e185392f6462e2676a66 /board/yorp/gpio.inc
parent32b1e3add72159df481ea5e3d86b581ef07caaa3 (diff)
downloadchrome-ec-2c9c55da93f57ac8eaef47328239d8957fd4a5d6.tar.gz
octopus: implement device mode
To enable device mode, set the gpio USB2_OTG_ID in the respective boards to high. Pull the gpio low to disable device mode. BUG=b:79343083 BRANCH=NONE TEST=On Yorp board, for UFP mode gpio USB2_OTG_ID should be high, for DFP mode gpio USB2_OTG_ID should be low. In OS console, lspci should list xdci. (with chromiumos/third_party/coreboot/+/1064592) Change-Id: I70f13a9705626d9bcbe989239f6826d35d8fa536 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1058832 Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'board/yorp/gpio.inc')
-rw-r--r--board/yorp/gpio.inc2
1 files changed, 2 insertions, 0 deletions
diff --git a/board/yorp/gpio.inc b/board/yorp/gpio.inc
index ec4e084bd3..8ce745de0b 100644
--- a/board/yorp/gpio.inc
+++ b/board/yorp/gpio.inc
@@ -99,6 +99,8 @@ GPIO(I2C7_SDA, PIN(B, 2), GPIO_INPUT |
/* USB pins */
GPIO(EN_USB_A_5V, PIN(6, 7), GPIO_OUT_LOW) /* Enable A0/A1 5V Charging */
+/* OTG pin - This pin will be changed to PIN(8,3) in Proto 2*/
+GPIO(USB2_OTG_ID, PIN(A, 0), GPIO_OUT_LOW) /* OTG ID */
GPIO(USB_A_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH) /* Enable A0/A1 1.5A Charging */
/* TODO(b/74254366): Break out A1 signals once they are there in HW */
/* USB_C0_PD_RST_L isn't connected to PIN(6,2) since ANX TCPC doesn't have reset */