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authorGwendal Grignou <gwendal@chromium.org>2019-03-11 15:57:52 -0700
committerchrome-bot <chrome-bot@chromium.org>2019-03-26 04:42:55 -0700
commitbb266fc26fc05d4ab22de6ad7bce5b477c9f9140 (patch)
treef6ada087f62246c3a9547e649ac8846b0ed6d5ab /board/zinger/usb_pd_config.h
parent0bfc511527cf2aebfa163c63a1d028419ca0b0c3 (diff)
downloadchrome-ec-bb266fc26fc05d4ab22de6ad7bce5b477c9f9140.tar.gz
common: replace 1 << digits, with BIT(digits)
Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'board/zinger/usb_pd_config.h')
-rw-r--r--board/zinger/usb_pd_config.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/board/zinger/usb_pd_config.h b/board/zinger/usb_pd_config.h
index fbe24e0003..2a7e0e7f7d 100644
--- a/board/zinger/usb_pd_config.h
+++ b/board/zinger/usb_pd_config.h
@@ -47,7 +47,7 @@ static inline void spi_enable_clock(int port)
#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
/* connect TIM3 CH1 to TIM3_CH2 input */
#define TIM_CCR_CS 2
-#define EXTI_COMP_MASK(p) (1 << 7)
+#define EXTI_COMP_MASK(p) BIT(7)
#define IRQ_COMP STM32_IRQ_EXTI4_15
/* the RX is inverted, triggers on rising edge */
#define EXTI_XTSR STM32_EXTI_RTSR
@@ -64,8 +64,8 @@ static inline void pd_set_pins_speed(int port)
static inline void pd_tx_spi_reset(int port)
{
/* Reset SPI1 */
- STM32_RCC_APB2RSTR |= (1 << 12);
- STM32_RCC_APB2RSTR &= ~(1 << 12);
+ STM32_RCC_APB2RSTR |= BIT(12);
+ STM32_RCC_APB2RSTR &= ~BIT(12);
}
/* Drive the CC line from the TX block */
@@ -81,7 +81,7 @@ static inline void pd_tx_enable(int port, int polarity)
static inline void pd_tx_disable(int port, int polarity)
{
/* Put TX GND (PA4) in Hi-Z state */
- STM32_GPIO_BSRR(GPIO_A) = 1 << 4 /* Set */;
+ STM32_GPIO_BSRR(GPIO_A) = BIT(4) /* Set */;
/* Put SPI MISO (PA6) in Hi-Z by putting it in input mode */
STM32_GPIO_MODER(GPIO_A) &= ~(0x3 << (2*6));
}