samus: pd: dual USB-PD port support for samus

Adds dual USB-PD port support for samus. Both ports are in dual-role
and can perform either role.

Both ports work fine when only one of the ports is in use. But,
still having problems with PD errors on the lower priority port (port
0). If you have a charger plugged into port 0, and a type-C USB dongle
plugged into port 1, then port 1 has higher priority, and in the
SRC_DISCONNECTED state, every 1.5 seconds when it sends source cap
packet, we occasionally drop pings on port 0, which results in a
lot of start/stop charging.

BUG=chrome-os-partner:28585
BRANCH=none
TEST=Tested on samus to make sure both ports work when I
plug in a charger and a type-C USB dongle with a pull-down on the CC
line. Tested on plankton and zinger to make sure PD works as expected.

Change-Id: Ie7bde3e258f5cd23a0b82b626c0993a45b0df074
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/200750
Reviewed-by: Vic Yang <victoryang@chromium.org>
Tested-by: Vic Yang <victoryang@chromium.org>

1 files changed, 38 insertions, 16 deletions

diff --git a/board/zinger/usb_pd_config.h b/board/zinger/usb_pd_config.h
index 73959ff787..cbaa8b286b 100644
--- a/board/zinger/usb_pd_config.h
+++ b/board/zinger/usb_pd_config.h
@@ -8,43 +8,65 @@
 #ifndef __USB_PD_CONFIG_H
 #define __USB_PD_CONFIG_H
 
+/* Port and task configuration */
+#define PD_PORT_COUNT 1
+/* Stub value */
+#define TASK_ID_PD 0
+#define PORT_TO_TASK_ID(port) TASK_ID_PD
+#define TASK_ID_TO_PORT(id)   0
+
 /* Timer selection for baseband PD communication */
-#define TIM_CLOCK_PD_TX 14
-#define TIM_CLOCK_PD_RX  3
+#define TIM_CLOCK_PD_TX_C0 14
+#define TIM_CLOCK_PD_RX_C0  3
+
+#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0
+#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0
+
+/* Timer channel */
+#define TIM_RX_CCR_C0 1
+
+/* RX timer capture/compare register */
+#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
+#define TIM_RX_CCR_REG(p) TIM_CCR_C0
+
+/* TX and RX timer register */
+#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0))
+#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0))
+#define TIM_REG_TX(p) TIM_REG_TX_C0
+#define TIM_REG_RX(p) TIM_REG_RX_C0
 
 /* use the hardware accelerator for CRC */
 #define CONFIG_HW_CRC
 
 /* TX is using SPI1 on PA4-6 */
-#define SPI_REGS STM32_SPI1_REGS
-#define DMAC_SPI_TX STM32_DMAC_CH3
+#define SPI_REGS(p) STM32_SPI1_REGS
 
-static inline void spi_enable_clock(void)
+static inline void spi_enable_clock(int port)
 {
 	/* Already done in hardware_init() */
 }
 
+#define DMAC_SPI_TX(p) STM32_DMAC_CH3
+
 /* RX is on TIM3 CH1 connected to TIM3 CH2 pin (PA7, not internal COMP) */
-#define DMAC_TIM_RX STM32_DMAC_CH4
-#define TIM_CCR_IDX 1
+#define TIM_CCR_IDX(p) TIM_RX_CCR_C0
 /* connect TIM3 CH1 to TIM3_CH2 input */
 #define TIM_CCR_CS  2
-#define EXTI_COMP_MASK (1 << 7)
+#define EXTI_COMP_MASK(p) (1 << 7)
 #define IRQ_COMP STM32_IRQ_EXTI4_15
 /* the RX is inverted, triggers on rising edge */
 #define EXTI_XTSR STM32_EXTI_RTSR
 
-/* Clock divider for RX edges timings (2.4Mhz counter from 48Mhz clock) */
-#define RX_CLOCK_DIV (20 - 1)
+#define DMAC_TIM_RX(p) STM32_DMAC_CH4
 
 /* the pins used for communication need to be hi-speed */
-static inline void pd_set_pins_speed(void)
+static inline void pd_set_pins_speed(int port)
 {
 	/* Already done in hardware_init() */
 }
 
 /* Reset SPI peripheral used for TX */
-static inline void pd_tx_spi_reset(void)
+static inline void pd_tx_spi_reset(int port)
 {
 	/* Reset SPI1 */
 	STM32_RCC_APB2RSTR |= (1 << 12);
@@ -52,7 +74,7 @@ static inline void pd_tx_spi_reset(void)
 }
 
 /* Drive the CC line from the TX block */
-static inline void pd_tx_enable(int polarity)
+static inline void pd_tx_enable(int port, int polarity)
 {
 	/* Drive SPI MISO on PA6 by putting it in AF mode  */
 	STM32_GPIO_MODER(GPIO_A) |= 0x2 << (2*6);
@@ -61,7 +83,7 @@ static inline void pd_tx_enable(int polarity)
 }
 
 /* Put the TX driver in Hi-Z state */
-static inline void pd_tx_disable(int polarity)
+static inline void pd_tx_disable(int port, int polarity)
 {
 	/* Put TX GND (PA4) in Hi-Z state */
 	STM32_GPIO_BSRR(GPIO_A) = 1 << 4 /* Set */;
@@ -70,7 +92,7 @@ static inline void pd_tx_disable(int polarity)
 }
 
 /* we know the plug polarity, do the right configuration */
-static inline void pd_select_polarity(int polarity)
+static inline void pd_select_polarity(int port, int polarity)
 {
 	/* captive cable : no polarity */
 }
@@ -81,7 +103,7 @@ static inline void pd_tx_init(void)
 	/* Already done in hardware_init() */
 }
 
-static inline int pd_adc_read(int cc)
+static inline int pd_adc_read(int port, int cc)
 {
 	if (cc == 0)
 		return adc_read_channel(ADC_CH_CC1_PD);