diff options
author | Gwendal Grignou <gwendal@chromium.org> | 2019-03-11 15:57:52 -0700 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2019-03-26 04:42:55 -0700 |
commit | bb266fc26fc05d4ab22de6ad7bce5b477c9f9140 (patch) | |
tree | f6ada087f62246c3a9547e649ac8846b0ed6d5ab /board/zinger | |
parent | 0bfc511527cf2aebfa163c63a1d028419ca0b0c3 (diff) | |
download | chrome-ec-bb266fc26fc05d4ab22de6ad7bce5b477c9f9140.tar.gz |
common: replace 1 << digits, with BIT(digits)
Requested for linux integration, use BIT instead of 1 <<
First step replace bit operation with operand containing only digits.
Fix an error in motion_lid try to set bit 31 of a signed integer.
BUG=None
BRANCH=None
TEST=compile
Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518659
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'board/zinger')
-rw-r--r-- | board/zinger/hardware.c | 46 | ||||
-rw-r--r-- | board/zinger/runtime.c | 10 | ||||
-rw-r--r-- | board/zinger/usb_pd_config.h | 8 | ||||
-rw-r--r-- | board/zinger/usb_pd_policy.c | 2 |
4 files changed, 33 insertions, 33 deletions
diff --git a/board/zinger/hardware.c b/board/zinger/hardware.c index c3cf2b5f4a..1d2ffb1eb3 100644 --- a/board/zinger/hardware.c +++ b/board/zinger/hardware.c @@ -17,12 +17,12 @@ static void system_init(void) { /* Enable access to RCC CSR register and RTC backup registers */ - STM32_PWR_CR |= 1 << 8; + STM32_PWR_CR |= BIT(8); /* switch on LSI */ - STM32_RCC_CSR |= 1 << 0; + STM32_RCC_CSR |= BIT(0); /* Wait for LSI to be ready */ - while (!(STM32_RCC_CSR & (1 << 1))) + while (!(STM32_RCC_CSR & BIT(1))) ; /* re-configure RTC if needed */ if ((STM32_RCC_BDCR & 0x00018300) != 0x00008200) { @@ -108,7 +108,7 @@ static void adc_init(void) ; } /* Single conversion, right aligned, 12-bit */ - STM32_ADC_CFGR1 = 1 << 12; /* (1 << 15) => AUTOOFF */; + STM32_ADC_CFGR1 = BIT(12); /* BIT(15) => AUTOOFF */; /* clock is ADCCLK (ADEN must be off when writing this reg) */ STM32_ADC_CFGR2 = 0; /* Sampling time : 71.5 ADC clock cycles, about 5us */ @@ -172,9 +172,9 @@ void hardware_init(void) power_init(); /* Clear the hardware reset cause by setting the RMVF bit */ - STM32_RCC_CSR |= 1 << 24; + STM32_RCC_CSR |= BIT(24); /* Clear SBF in PWR_CSR */ - STM32_PWR_CR |= 1 << 3; + STM32_PWR_CR |= BIT(3); /* * WORKAROUND: as we cannot de-activate the watchdog during @@ -206,7 +206,7 @@ static int adc_enable_last_watchdog(void) static inline int adc_watchdog_enabled(void) { - return STM32_ADC_CFGR1 & (1 << 23); + return STM32_ADC_CFGR1 & BIT(23); } int adc_read_channel(enum adc_channel ch) @@ -222,9 +222,9 @@ int adc_read_channel(enum adc_channel ch) /* Clear flags */ STM32_ADC_ISR = 0x8e; /* Start conversion */ - STM32_ADC_CR |= 1 << 2; /* ADSTART */ + STM32_ADC_CR |= BIT(2); /* ADSTART */ /* Wait for end of conversion */ - while (!(STM32_ADC_ISR & (1 << 2))) + while (!(STM32_ADC_ISR & BIT(2))) ; /* read converted value */ value = STM32_ADC_DR; @@ -249,12 +249,12 @@ int adc_enable_watchdog(int ch, int high, int low) /* Clear flags */ STM32_ADC_ISR = 0x8e; /* Set Watchdog enable bit on a single channel / continuous mode */ - STM32_ADC_CFGR1 = (ch << 26) | (1 << 23) | (1 << 22) - | (1 << 13) | (1 << 12); + STM32_ADC_CFGR1 = (ch << 26) | BIT(23) | BIT(22) + | BIT(13) | BIT(12); /* Enable watchdog interrupt */ - STM32_ADC_IER = 1 << 7; + STM32_ADC_IER = BIT(7); /* Start continuous conversion */ - STM32_ADC_CR |= 1 << 2; /* ADSTART */ + STM32_ADC_CR |= BIT(2); /* ADSTART */ return EC_SUCCESS; } @@ -262,12 +262,12 @@ int adc_enable_watchdog(int ch, int high, int low) int adc_disable_watchdog(void) { /* Stop on-going conversion */ - STM32_ADC_CR |= 1 << 4; /* ADSTP */ + STM32_ADC_CR |= BIT(4); /* ADSTP */ /* Wait for conversion to stop */ - while (STM32_ADC_CR & (1 << 4)) + while (STM32_ADC_CR & BIT(4)) ; /* CONT=0 -> continuous mode off / Clear Watchdog enable */ - STM32_ADC_CFGR1 = 1 << 12; + STM32_ADC_CFGR1 = BIT(12); /* Disable interrupt */ STM32_ADC_IER = 0; /* Clear flags */ @@ -294,13 +294,13 @@ int adc_disable_watchdog(void) #define KEY2 0xCDEF89AB /* Lock bits for FLASH_CR register */ -#define PG (1<<0) -#define PER (1<<1) -#define OPTPG (1<<4) -#define OPTER (1<<5) -#define STRT (1<<6) -#define CR_LOCK (1<<7) -#define OPTWRE (1<<9) +#define PG BIT(0) +#define PER BIT(1) +#define OPTPG BIT(4) +#define OPTER BIT(5) +#define STRT BIT(6) +#define CR_LOCK BIT(7) +#define OPTWRE BIT(9) int flash_physical_write(int offset, int size, const char *data) { diff --git a/board/zinger/runtime.c b/board/zinger/runtime.c index f92b919398..9e883888af 100644 --- a/board/zinger/runtime.c +++ b/board/zinger/runtime.c @@ -94,19 +94,19 @@ DECLARE_IRQ(STM32_IRQ_TIM2, tim2_interrupt, 1); static void zinger_config_hispeed_clock(void) { /* Ensure that HSI8 is ON */ - if (!(STM32_RCC_CR & (1 << 1))) { + if (!(STM32_RCC_CR & BIT(1))) { /* Enable HSI */ - STM32_RCC_CR |= 1 << 0; + STM32_RCC_CR |= BIT(0); /* Wait for HSI to be ready */ - while (!(STM32_RCC_CR & (1 << 1))) + while (!(STM32_RCC_CR & BIT(1))) ; } /* PLLSRC = HSI, PLLMUL = x12 (x HSI/2) = 48Mhz */ STM32_RCC_CFGR = 0x00288000; /* Enable PLL */ - STM32_RCC_CR |= 1 << 24; + STM32_RCC_CR |= BIT(24); /* Wait for PLL to be ready */ - while (!(STM32_RCC_CR & (1 << 25))) + while (!(STM32_RCC_CR & BIT(25))) ; /* switch SYSCLK to PLL */ diff --git a/board/zinger/usb_pd_config.h b/board/zinger/usb_pd_config.h index fbe24e0003..2a7e0e7f7d 100644 --- a/board/zinger/usb_pd_config.h +++ b/board/zinger/usb_pd_config.h @@ -47,7 +47,7 @@ static inline void spi_enable_clock(int port) #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0 /* connect TIM3 CH1 to TIM3_CH2 input */ #define TIM_CCR_CS 2 -#define EXTI_COMP_MASK(p) (1 << 7) +#define EXTI_COMP_MASK(p) BIT(7) #define IRQ_COMP STM32_IRQ_EXTI4_15 /* the RX is inverted, triggers on rising edge */ #define EXTI_XTSR STM32_EXTI_RTSR @@ -64,8 +64,8 @@ static inline void pd_set_pins_speed(int port) static inline void pd_tx_spi_reset(int port) { /* Reset SPI1 */ - STM32_RCC_APB2RSTR |= (1 << 12); - STM32_RCC_APB2RSTR &= ~(1 << 12); + STM32_RCC_APB2RSTR |= BIT(12); + STM32_RCC_APB2RSTR &= ~BIT(12); } /* Drive the CC line from the TX block */ @@ -81,7 +81,7 @@ static inline void pd_tx_enable(int port, int polarity) static inline void pd_tx_disable(int port, int polarity) { /* Put TX GND (PA4) in Hi-Z state */ - STM32_GPIO_BSRR(GPIO_A) = 1 << 4 /* Set */; + STM32_GPIO_BSRR(GPIO_A) = BIT(4) /* Set */; /* Put SPI MISO (PA6) in Hi-Z by putting it in input mode */ STM32_GPIO_MODER(GPIO_A) &= ~(0x3 << (2*6)); } diff --git a/board/zinger/usb_pd_policy.c b/board/zinger/usb_pd_policy.c index c210ce9cea..07782c4f3b 100644 --- a/board/zinger/usb_pd_policy.c +++ b/board/zinger/usb_pd_policy.c @@ -70,7 +70,7 @@ static enum faults fault; static timestamp_t fault_deadline; /* ADC in 12-bit mode */ -#define ADC_SCALE (1 << 12) +#define ADC_SCALE BIT(12) /* ADC power supply : VDDA = 3.3V */ #define VDDA_MV 3300 /* Current sense resistor : 5 milliOhm */ |