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| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-09-04 19:09:33 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-09-16 14:49:31 -0700 |
| commit | d58e54730c03290296df5bb65cb84264e4b2facc (patch) | |
| tree | d736570c84a0e9737b8881ec68b073327a5c2ae5 /board/zinger | |
| parent | 4b3c13ddfefd229dde49fb4cbf5a6bfc49f64973 (diff) | |
| download | chrome-ec-d58e54730c03290296df5bb65cb84264e4b2facc.tar.gz | |
cleanup: Rename geometry constants
Rename and add geometry constants to match spec doc -
https://goo.gl/fnzTvr.
CONFIG_FLASH_BASE becomes CONFIG_PROGRAM_MEMORY_BASE
CONFIG_FLASH_MAPPED becomes CONFIG_MAPPED_STORAGE
Add CONFIG_INTERNAL_STORAGE, CONFIG_EXTERNAL_STORAGE and
CONFIG_MAPPED_STORAGE_BASE where appropriate.
This CL leaves chip/npcx in a broken state -- it's fixed in a follow-up
CL.
BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images
Change-Id: Idb3c4ed9f7f6edd0a6d49ad11753eba713e67a80
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/297484
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'board/zinger')
| -rw-r--r-- | board/zinger/board.c | 7 | ||||
| -rw-r--r-- | board/zinger/hardware.c | 6 |
2 files changed, 7 insertions, 6 deletions
diff --git a/board/zinger/board.c b/board/zinger/board.c index 5f1201ea76..f7552523a5 100644 --- a/board/zinger/board.c +++ b/board/zinger/board.c @@ -20,8 +20,9 @@ const struct rsa_public_key pkey __attribute__((section(".rsa_pubkey"))) = #include "gen_pub_key.h" /* The RSA signature is stored at the end of the RW firmware */ -static const void *rw_sig = (void *)CONFIG_FLASH_BASE + CONFIG_RW_MEM_OFF - + CONFIG_RW_SIZE - RSANUMBYTES; +static const void *rw_sig = (void *)CONFIG_PROGRAM_MEMORY_BASE + + CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE - + RSANUMBYTES; /* Large 768-Byte buffer for RSA computation : could be re-use afterwards... */ static uint32_t rsa_workbuf[3 * RSANUMWORDS]; @@ -29,7 +30,7 @@ extern void pd_rx_handler(void); /* RW firmware reset vector */ static uint32_t * const rw_rst = - (uint32_t *)(CONFIG_FLASH_BASE+CONFIG_RW_MEM_OFF+4); + (uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE+CONFIG_RW_MEM_OFF+4); /* External interrupt EXTINT7 for external comparator on PA7 */ void pd_rx_interrupt(void) diff --git a/board/zinger/hardware.c b/board/zinger/hardware.c index 31f57da6a3..d6a8d1d4c3 100644 --- a/board/zinger/hardware.c +++ b/board/zinger/hardware.c @@ -304,11 +304,11 @@ int adc_disable_watchdog(void) int flash_physical_write(int offset, int size, const char *data) { - uint16_t *address = (uint16_t *)(CONFIG_FLASH_BASE + offset); + uint16_t *address = (uint16_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset); int res = EC_SUCCESS; int i; - if ((uint32_t)address > CONFIG_FLASH_BASE + CONFIG_FLASH_SIZE) + if ((uint32_t)address > CONFIG_PROGRAM_MEMORY_BASE + CONFIG_FLASH_SIZE) return EC_ERROR_INVAL; /* unlock CR if needed */ @@ -372,7 +372,7 @@ int flash_physical_erase(int offset, int size) offset += CONFIG_FLASH_ERASE_SIZE) { int i; /* select page to erase */ - STM32_FLASH_AR = CONFIG_FLASH_BASE + offset; + STM32_FLASH_AR = CONFIG_PROGRAM_MEMORY_BASE + offset; /* set STRT bit : start erase */ STM32_FLASH_CR |= STRT; |