diff options
author | Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> | 2021-06-08 09:18:19 +0800 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2021-06-18 02:46:22 +0000 |
commit | 69b9b9d7e74e6aed462a3df154c8a0e6fd0ae128 (patch) | |
tree | e15848b98da8817cd1e71f75c455a11b8e91f120 /board | |
parent | 8317b1136aaf03aa6988e98300b50cebb90e8de7 (diff) | |
download | chrome-ec-69b9b9d7e74e6aed462a3df154c8a0e6fd0ae128.tar.gz |
gimble: Initial EC image
Create the initial EC image for the gimble variant by copying
the brya reference board EC files into a new directory named for
the variant.
(Auto-Generated by create_initial_ec_image.sh version 1.5.0).
BUG=b:190334274
BRANCH=None
TEST=make BOARD=gimble
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ia740667582e0f53bfc6afb37d23edf8c2d1d543e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2944517
Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Diffstat (limited to 'board')
-rw-r--r-- | board/gimble/battery.c | 98 | ||||
-rw-r--r-- | board/gimble/board.c | 160 | ||||
-rw-r--r-- | board/gimble/board.h | 266 | ||||
-rw-r--r-- | board/gimble/build.mk | 25 | ||||
-rw-r--r-- | board/gimble/ec.tasklist | 31 | ||||
-rw-r--r-- | board/gimble/fans.c | 88 | ||||
-rw-r--r-- | board/gimble/fw_config.c | 59 | ||||
-rw-r--r-- | board/gimble/fw_config.h | 54 | ||||
-rw-r--r-- | board/gimble/gpio.inc | 164 | ||||
-rw-r--r-- | board/gimble/i2c.c | 77 | ||||
-rw-r--r-- | board/gimble/keyboard.c | 25 | ||||
-rw-r--r-- | board/gimble/led.c | 90 | ||||
-rw-r--r-- | board/gimble/pwm.c | 70 | ||||
-rw-r--r-- | board/gimble/sensors.c | 321 | ||||
-rw-r--r-- | board/gimble/tune_mp2964.c | 41 | ||||
-rw-r--r-- | board/gimble/usbc_config.c | 389 | ||||
-rw-r--r-- | board/gimble/usbc_config.h | 22 | ||||
-rw-r--r-- | board/gimble/vif_override.xml | 3 |
18 files changed, 1983 insertions, 0 deletions
diff --git a/board/gimble/battery.c b/board/gimble/battery.c new file mode 100644 index 0000000000..91ecfe0583 --- /dev/null +++ b/board/gimble/battery.c @@ -0,0 +1,98 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Battery pack vendor provided charging profile + */ + +#include "battery_fuel_gauge.h" +#include "common.h" +#include "util.h" + +/* + * Battery info for all Brya battery types. Note that the fields + * start_charging_min/max and charging_min/max are not used for the charger. + * The effective temperature limits are given by discharging_min/max_c. + * + * Fuel Gauge (FG) parameters which are used for determining if the battery + * is connected, the appropriate ship mode (battery cutoff) command, and the + * charge/discharge FETs status. + * + * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery + * register. For some batteries, the charge/discharge FET bits are set when + * charging/discharging is active, in other types, these bits set mean that + * charging/discharging is disabled. Therefore, in addition to the mask for + * these bits, a disconnect value must be specified. Note that for TI fuel + * gauge, the charge/discharge FET status is found in Operation Status (0x54), + * but a read of Manufacturer Access (0x00) will return the lower 16 bits of + * Operation status which contains the FET status bits. + * + * The assumption for battery types supported is that the charge/discharge FET + * status can be read with a sb_read() command and therefore, only the register + * address, mask, and disconnect value need to be provided. + */ +const struct board_batt_params board_battery_info[] = { + /* POW-TECH GQA05 Battery Information */ + [BATTERY_POWER_TECH] = { + /* BQ40Z50 Fuel Gauge */ + .fuel_gauge = { + .manuf_name = "POW-TECH", + .device_name = "BATGQA05L22", + .ship_mode = { + .reg_addr = 0x00, + .reg_data = { 0x0010, 0x0010 }, + }, + .fet = { + .mfgacc_support = 1, + .reg_addr = 0x00, + .reg_mask = 0x2000, /* XDSG */ + .disconnect_val = 0x2000, + } + }, + .batt_info = { + .voltage_max = TARGET_WITH_MARGIN(13050, 5), + .voltage_normal = 11400, /* mV */ + .voltage_min = 9000, /* mV */ + .precharge_current = 280, /* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 45, + .charging_min_c = 0, + .charging_max_c = 45, + .discharging_min_c = -10, + .discharging_max_c = 60, + }, + }, + /* LGC L17L3PB0 Battery Information */ + /* + * Battery info provided by ODM on b/143477210, comment #11 + */ + [BATTERY_LGC011] = { + .fuel_gauge = { + .manuf_name = "LGC", + .ship_mode = { + .reg_addr = 0x00, + .reg_data = { 0x0010, 0x0010 }, + }, + .fet = { + .reg_addr = 0x0, + .reg_mask = 0x6000, + .disconnect_val = 0x6000, + } + }, + .batt_info = { + .voltage_max = TARGET_WITH_MARGIN(13200, 5), + .voltage_normal = 11550, /* mV */ + .voltage_min = 9000, /* mV */ + .precharge_current = 256, /* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 45, + .charging_min_c = 0, + .charging_max_c = 60, + .discharging_min_c = 0, + .discharging_max_c = 75, + }, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT); + +const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_POWER_TECH; diff --git a/board/gimble/board.c b/board/gimble/board.c new file mode 100644 index 0000000000..eaac2ad278 --- /dev/null +++ b/board/gimble/board.c @@ -0,0 +1,160 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" + +#include "battery.h" +#include "button.h" +#include "charge_ramp.h" +#include "charger.h" +#include "console.h" +#include "driver/accel_lis2dw12.h" +#include "driver/accelgyro_lsm6dso.h" +#include "driver/als_tcs3400.h" +#include "fw_config.h" +#include "hooks.h" +#include "lid_switch.h" +#include "power_button.h" +#include "power.h" +#include "switch.h" +#include "tablet_mode.h" +#include "throttle_ap.h" + +#include "gpio_list.h" /* Must come after other header files. */ + +/* Console output macros */ +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) + +/******************************************************************************/ +/* USB-A charging control */ + +const int usb_port_enable[USB_PORT_COUNT] = { + GPIO_EN_PP5000_USBA_R, +}; +BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT); + +/******************************************************************************/ + +__override void board_cbi_init(void) +{ + config_usb_db_type(); +} + +/* Called on AP S3 -> S0 transition */ +static void board_chipset_resume(void) +{ + /* Allow keyboard backlight to be enabled */ + + if (get_board_id() == 1) + gpio_set_level(GPIO_ID_1_EC_KB_BL_EN, 1); + else + gpio_set_level(GPIO_EC_KB_BL_EN_L, 0); +} +DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT); + +/* Called on AP S0 -> S3 transition */ +static void board_chipset_suspend(void) +{ + /* Turn off the keyboard backlight if it's on. */ + + if (get_board_id() == 1) + gpio_set_level(GPIO_ID_1_EC_KB_BL_EN, 0); + else + gpio_set_level(GPIO_EC_KB_BL_EN_L, 1); +} +DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); + +#ifdef CONFIG_CHARGE_RAMP_SW + +/* + * TODO(b/181508008): tune this threshold + */ + +#define BC12_MIN_VOLTAGE 4400 + +/** + * Return true if VBUS is too low + */ +int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) +{ + int voltage; + + if (charger_get_vbus_voltage(port, &voltage)) + voltage = 0; + + if (voltage == 0) { + CPRINTS("%s: must be disconnected", __func__); + return 1; + } + + if (voltage < BC12_MIN_VOLTAGE) { + CPRINTS("%s: port %d: vbus %d lower than %d", __func__, + port, voltage, BC12_MIN_VOLTAGE); + return 1; + } + + return 0; +} + +#endif /* CONFIG_CHARGE_RAMP_SW */ + +enum battery_present battery_hw_present(void) +{ + enum gpio_signal batt_pres; + + if (get_board_id() == 1) + batt_pres = GPIO_ID_1_EC_BATT_PRES_ODL; + else + batt_pres = GPIO_EC_BATT_PRES_ODL; + + /* The GPIO is low when the battery is physically present */ + return gpio_get_level(batt_pres) ? BP_NO : BP_YES; +} + +/* + * Explicitly apply the board ID 1 *gpio.inc settings to pins that + * were reassigned on current boards. + */ + +static void set_board_id_1_gpios(void) +{ + if (get_board_id() != 1) + return; + + gpio_set_flags(GPIO_ID_1_EC_KB_BL_EN, GPIO_OUT_LOW); +} +DECLARE_HOOK(HOOK_INIT, set_board_id_1_gpios, HOOK_PRIO_FIRST); + +/* + * Reclaim GPIO pins on board ID 1 that are used as ADC inputs on + * current boards. ALT function group MODULE_ADC pins are set in + * HOOK_PRIO_INIT_ADC and can be reclaimed right after the hook runs. + */ + +static void board_id_1_reclaim_adc(void) +{ + if (get_board_id() != 1) + return; + + /* + * GPIO_ID_1_USB_C0_C2_TCPC_RST_ODL is on GPIO34 + * + * The TCPC has already been reset by board_tcpc_init() executed + * from HOOK_PRIO_INIT_CHIPSET. Later, the pin gets set to ADC6 + * in HOOK_PRIO_INIT_ADC, so we simply need to set the pin back + * to GPIO34. + */ + gpio_set_flags(GPIO_ID_1_USB_C0_C2_TCPC_RST_ODL, GPIO_ODR_HIGH); + gpio_set_alternate_function(GPIO_PORT_3, BIT(4), GPIO_ALT_FUNC_NONE); + + /* + * The pin gets set to ADC7 in HOOK_PRIO_INIT_ADC, so we simply + * need to set it back to GPIOE1. + */ + gpio_set_flags(GPIO_ID_1_EC_BATT_PRES_ODL, GPIO_INPUT); + gpio_set_alternate_function(GPIO_PORT_E, BIT(1), GPIO_ALT_FUNC_NONE); +} +DECLARE_HOOK(HOOK_INIT, board_id_1_reclaim_adc, HOOK_PRIO_INIT_ADC + 1); diff --git a/board/gimble/board.h b/board/gimble/board.h new file mode 100644 index 0000000000..5eb4d1e1ff --- /dev/null +++ b/board/gimble/board.h @@ -0,0 +1,266 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Brya board configuration */ + +#ifndef __CROS_EC_BOARD_H +#define __CROS_EC_BOARD_H + +/* + * Early brya boards are not set up for vivaldi + */ +#undef CONFIG_KEYBOARD_VIVALDI + +/* Baseboard features */ +#include "baseboard.h" + +/* + * This will happen automatically on NPCX9 ES2 and later. Do not remove + * until we can confirm all earlier chips are out of service. + */ +#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP + +#define CONFIG_MP2964 + +/* LED */ +#define CONFIG_LED_PWM +#define CONFIG_LED_PWM_COUNT 2 +#undef CONFIG_LED_PWM_NEAR_FULL_COLOR +#undef CONFIG_LED_PWM_SOC_ON_COLOR +#undef CONFIG_LED_PWM_SOC_SUSPEND_COLOR +#undef CONFIG_LED_PWM_LOW_BATT_COLOR +#define CONFIG_LED_PWM_NEAR_FULL_COLOR EC_LED_COLOR_WHITE +#define CONFIG_LED_PWM_SOC_ON_COLOR EC_LED_COLOR_WHITE +#define CONFIG_LED_PWM_SOC_SUSPEND_COLOR EC_LED_COLOR_WHITE +#define CONFIG_LED_PWM_LOW_BATT_COLOR EC_LED_COLOR_AMBER + +/* Sensors */ +#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */ +#define CONFIG_ACCEL_LSM6DSO_INT_EVENT \ + TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) + +/* TCS3400 ALS */ +#define CONFIG_ALS +#define ALS_COUNT 1 +#define CONFIG_ALS_TCS3400 +#define CONFIG_ALS_TCS3400_INT_EVENT \ + TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS) + +/* Enable sensor fifo, must also define the _SIZE and _THRES */ +#define CONFIG_ACCEL_FIFO +/* FIFO size is in power of 2. */ +#define CONFIG_ACCEL_FIFO_SIZE 256 +/* Depends on how fast the AP boots and typical ODRs */ +#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) + +/* Sensors without hardware FIFO are in forced mode */ +#define CONFIG_ACCEL_FORCE_MODE_MASK \ + (BIT(LID_ACCEL) | BIT(CLEAR_ALS)) + +/* Lid accel */ +#define CONFIG_LID_ANGLE +#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL +#define CONFIG_ACCEL_LIS2DWL +#define CONFIG_ACCEL_LIS2DW_AS_BASE +#define CONFIG_ACCEL_LIS2DW12_INT_EVENT \ + TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL) + +#define CONFIG_ACCEL_INTERRUPTS + +/* Sensor console commands */ +#define CONFIG_CMD_ACCELS +#define CONFIG_CMD_ACCEL_INFO + +/* USB Type A Features */ +#define USB_PORT_COUNT 1 +#define CONFIG_USB_PORT_POWER_DUMB + +/* USB Type C and USB PD defines */ +#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY + +#define CONFIG_IO_EXPANDER +#define CONFIG_IO_EXPANDER_NCT38XX +#define CONFIG_IO_EXPANDER_PORT_COUNT 2 + +#define CONFIG_USB_PD_TCPM_PS8815 +#define CONFIG_USBC_RETIMER_INTEL_BB + +#define CONFIG_USBC_PPC_SYV682X +#define CONFIG_USBC_PPC_NX20P3483 + +/* TODO: b/177608416 - measure and check these values on brya */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_VCONN_SWAP_DELAY 5000 /* us */ + +/* + * Passive USB-C cables only support up to 60W. + */ +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 + +/* + * Macros for GPIO signals used in common code that don't match the + * schematic names. Signal names in gpio.inc match the schematic and are + * then redefined here to so it's more clear which signal is being used for + * which purpose. + */ +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L + +/* + * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup + * signal. + */ +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG +#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK +#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL +#define GPIO_RSMRST_L_PGOOD GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_WP_L GPIO_EC_WP_ODL + +#define GPIO_ID_1_EC_KB_BL_EN GPIO_EC_BATT_PRES_ODL + +/* System has back-lit keyboard */ +#define CONFIG_PWM_KBLIGHT + +/* I2C Bus Configuration */ + +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 + +#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 + +#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 + +#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 + +#define I2C_PORT_USB_C0_C2_MUX NPCX_I2C_PORT3_0 +#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 + +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 + +#define I2C_ADDR_EEPROM_FLAGS 0x50 + +#define I2C_ADDR_MP2964_FLAGS 0x20 + +/* + * see b/174768555#comment22 + */ +#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56 +#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x57 + +/* Enabling Thunderbolt-compatible mode */ +#define CONFIG_USB_PD_TBT_COMPAT_MODE + +/* Enabling USB4 mode */ +#define CONFIG_USB_PD_USB4 + +/* Retimer */ +#define CONFIG_USBC_RETIMER_FW_UPDATE + +/* Thermal features */ +#define CONFIG_THERMISTOR +#define CONFIG_TEMP_SENSOR +#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_SEQ_EC_DSW_PWROK +#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B + +/* + * TODO(b/181271666): no fan control loop until sensors are tuned + */ +/* #define CONFIG_FANS FAN_CH_COUNT */ + +/* Charger defines */ +#define CONFIG_CHARGER_BQ25720 +#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70 +#define CONFIG_CHARGE_RAMP_SW +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 + +#ifndef __ASSEMBLER__ + +#include "gpio_signal.h" /* needed by registers.h */ +#include "registers.h" +#include "usbc_config.h" + +enum adc_channel { + ADC_TEMP_SENSOR_1_DDR_SOC, + ADC_TEMP_SENSOR_2_CHARGER, + ADC_CH_COUNT +}; + +enum temp_sensor_id { + TEMP_SENSOR_1_DDR_SOC, + TEMP_SENSOR_2_CHARGER, + TEMP_SENSOR_COUNT +}; + +enum sensor_id { + LID_ACCEL = 0, + BASE_ACCEL, + BASE_GYRO, + CLEAR_ALS, + RGB_ALS, + SENSOR_COUNT +}; + +enum ioex_port { + IOEX_C0_NCT38XX = 0, + IOEX_C2_NCT38XX, + IOEX_PORT_COUNT +}; + +enum battery_type { + BATTERY_POWER_TECH, + BATTERY_LGC011, + BATTERY_TYPE_COUNT +}; + +enum pwm_channel { + PWM_CH_LED2 = 0, /* PWM0 (white charger) */ + PWM_CH_LED3, /* PWM1 (orange on DB) */ + PWM_CH_LED1, /* PWM2 (orange charger) */ + PWM_CH_KBLIGHT, /* PWM3 */ + PWM_CH_FAN, /* PWM5 */ + PWM_CH_LED4, /* PWM7 (white on DB) */ + PWM_CH_COUNT +}; + +enum fan_channel { + FAN_CH_0 = 0, + FAN_CH_COUNT +}; + +enum mft_channel { + MFT_CH_0 = 0, + MFT_CH_COUNT +}; + +#endif /* !__ASSEMBLER__ */ + +#endif /* __CROS_EC_BOARD_H */ diff --git a/board/gimble/build.mk b/board/gimble/build.mk new file mode 100644 index 0000000000..78fee4583b --- /dev/null +++ b/board/gimble/build.mk @@ -0,0 +1,25 @@ +# -*- makefile -*- +# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Brya board specific files build +# + +CHIP:=npcx +CHIP_FAMILY:=npcx9 +CHIP_VARIANT:=npcx9m3f +BASEBOARD:=brya + +board-y= +board-y+=battery.o +board-y+=board.o +board-y+=fans.o +board-y+=fw_config.o +board-y+=i2c.o +board-y+=keyboard.o +board-y+=led.o +board-y+=pwm.o +board-y+=sensors.o +board-y+=tune_mp2964.o +board-y+=usbc_config.o diff --git a/board/gimble/ec.tasklist b/board/gimble/ec.tasklist new file mode 100644 index 0000000000..ef0aa84584 --- /dev/null +++ b/board/gimble/ec.tasklist @@ -0,0 +1,31 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * See CONFIG_TASK_LIST in config.h for details. + * + * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)). + * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x)) + */ + +#define CONFIG_TASK_LIST \ + TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \ + TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \ + TASK_ALWAYS(USB_CHG_P2, usb_charger_task, 0, TASK_STACK_SIZE) \ + TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \ + TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_C2, pd_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_INT_C0, pd_shared_alert_task, (BIT(2) | BIT(0)), TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE) diff --git a/board/gimble/fans.c b/board/gimble/fans.c new file mode 100644 index 0000000000..1427499e79 --- /dev/null +++ b/board/gimble/fans.c @@ -0,0 +1,88 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Physical fans. These are logically separate from pwm_channels. */ + +#include "common.h" +#include "console.h" +#include "fan_chip.h" +#include "fan.h" +#include "hooks.h" +#include "pwm_chip.h" +#include "pwm.h" + +/* MFT channels. These are logically separate from pwm_channels. */ +const struct mft_t mft_channels[] = { + [MFT_CH_0] = { + .module = NPCX_MFT_MODULE_1, + .clk_src = TCKC_LFCLK, + .pwm_id = PWM_CH_FAN, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); + +static const struct fan_conf fan_conf_0 = { + .flags = FAN_USE_RPM_MODE, + .ch = MFT_CH_0, /* Use MFT id to control fan */ + .pgood_gpio = -1, + .enable_gpio = GPIO_EN_PP5000_FAN, +}; + +/* + * TOOD(b/180681346): need to update for real fan + * + * Prototype fan spins at about 7200 RPM at 100% PWM. + * Set minimum at around 30% PWM. + */ +static const struct fan_rpm fan_rpm_0 = { + .rpm_min = 2200, + .rpm_start = 2200, + .rpm_max = 7200, +}; + +const struct fan_t fans[FAN_CH_COUNT] = { + [FAN_CH_0] = { + .conf = &fan_conf_0, + .rpm = &fan_rpm_0, + }, +}; + +#ifndef CONFIG_FANS + +/* + * TODO(b/181271666): use static fan speeds until fan and sensors are + * tuned. for now, use: + * + * AP off: 33% + * AP on: 100% + */ + +static void fan_slow(void) +{ + const int duty_pct = 33; + + ccprints("%s: speed %d%%", __func__, duty_pct); + + pwm_enable(PWM_CH_FAN, 1); + pwm_set_duty(PWM_CH_FAN, duty_pct); +} + +static void fan_max(void) +{ + const int duty_pct = 100; + + ccprints("%s: speed %d%%", __func__, duty_pct); + + pwm_enable(PWM_CH_FAN, 1); + pwm_set_duty(PWM_CH_FAN, duty_pct); +} + +DECLARE_HOOK(HOOK_INIT, fan_slow, HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, fan_slow, HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, fan_slow, HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_CHIPSET_RESET, fan_max, HOOK_PRIO_FIRST); +DECLARE_HOOK(HOOK_CHIPSET_RESUME, fan_max, HOOK_PRIO_DEFAULT); + +#endif /* CONFIG_FANS */ diff --git a/board/gimble/fw_config.c b/board/gimble/fw_config.c new file mode 100644 index 0000000000..2d9ee6de25 --- /dev/null +++ b/board/gimble/fw_config.c @@ -0,0 +1,59 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" +#include "console.h" +#include "cros_board_info.h" +#include "fw_config.h" + +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) + +static union brya_cbi_fw_config fw_config; +BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); + +/* + * FW_CONFIG defaults for brya if the CBI.FW_CONFIG data is not + * initialized. + */ +static const union brya_cbi_fw_config fw_config_defaults = { + .usb_db = DB_USB3_PS8815, + .kb_bl = KEYBOARD_BACKLIGHT_ENABLED, +}; + +/**************************************************************************** + * Brya FW_CONFIG access + */ +void board_init_fw_config(void) +{ + if (cbi_get_fw_config(&fw_config.raw_value)) { + CPRINTS("CBI: Read FW_CONFIG failed, using board defaults"); + fw_config = fw_config_defaults; + } + + if (get_board_id() == 0) { + /* + * Early boards have a zero'd out FW_CONFIG, so replace + * it with a sensible default value. If DB_USB_ABSENT2 + * was used as an alternate encoding of DB_USB_ABSENT to + * avoid the zero check, then fix it. + */ + if (fw_config.raw_value == 0) { + CPRINTS("CBI: FW_CONFIG is zero, using board defaults"); + fw_config = fw_config_defaults; + } else if (fw_config.usb_db == DB_USB_ABSENT2) { + fw_config.usb_db = DB_USB_ABSENT; + } + } +} + +union brya_cbi_fw_config get_fw_config(void) +{ + return fw_config; +} + +enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void) +{ + return fw_config.usb_db; +} diff --git a/board/gimble/fw_config.h b/board/gimble/fw_config.h new file mode 100644 index 0000000000..31843e759e --- /dev/null +++ b/board/gimble/fw_config.h @@ -0,0 +1,54 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __BOARD_BRYA_FW_CONFIG_H_ +#define __BOARD_BRYA_FW_CONFIG_H_ + +#include "stdint.h" + +/**************************************************************************** + * CBI FW_CONFIG layout for Brya board. + * + * Source of truth is the project/brya/brya/config.star configuration file. + */ + +enum ec_cfg_usb_db_type { + DB_USB_ABSENT = 0, + DB_USB3_PS8815 = 1, + DB_USB_ABSENT2 = 15 +}; + +enum ec_cfg_keyboard_backlight_type { + KEYBOARD_BACKLIGHT_DISABLED = 0, + KEYBOARD_BACKLIGHT_ENABLED = 1 +}; + +union brya_cbi_fw_config { + struct { + enum ec_cfg_usb_db_type usb_db : 4; + uint32_t sd_db : 2; + uint32_t lte_db : 1; + enum ec_cfg_keyboard_backlight_type kb_bl : 1; + uint32_t audio : 3; + uint32_t reserved_1 : 21; + }; + uint32_t raw_value; +}; + +/** + * Read the cached FW_CONFIG. Guaranteed to have valid values. + * + * @return the FW_CONFIG for the board. + */ +union brya_cbi_fw_config get_fw_config(void); + +/** + * Get the USB daughter board type from FW_CONFIG. + * + * @return the USB daughter board type. + */ +enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void); + +#endif /* __BOARD_BRYA_FW_CONFIG_H_ */ diff --git a/board/gimble/gpio.inc b/board/gimble/gpio.inc new file mode 100644 index 0000000000..1bf4cf2154 --- /dev/null +++ b/board/gimble/gpio.inc @@ -0,0 +1,164 @@ +/* -*- mode:c -*- + * + * Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#define MODULE_KB MODULE_KEYBOARD_SCAN + +/* INTERRUPT GPIOs: */ +GPIO_INT(ACOK_OD, PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt) +GPIO_INT(EC_ACCEL_INT_R_L, PIN(8, 1), GPIO_SEL_1P8V | GPIO_INT_FALLING, lis2dw12_interrupt) +GPIO_INT(EC_ALS_RGB_INT_R_L, PIN(D, 4), GPIO_INT_FALLING, tcs3400_interrupt) +GPIO_INT(EC_IMU_INT_R_L, PIN(5, 6), GPIO_SEL_1P8V | GPIO_INT_FALLING, lsm6dso_interrupt) +GPIO_INT(EC_PROCHOT_IN_L, PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt) +GPIO_INT(EC_VOLDN_BTN_ODL, PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) +GPIO_INT(EC_VOLUP_BTN_ODL, PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) +GPIO_INT(EC_WP_ODL, PIN(A, 1), GPIO_INT_BOTH, switch_interrupt) +GPIO_INT(GSC_EC_PWR_BTN_ODL, PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt) +GPIO_INT(LID_OPEN, PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt) +GPIO_INT(SEQ_EC_ALL_SYS_PG, PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(SEQ_EC_DSW_PWROK, PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(SEQ_EC_RSMRST_ODL, PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(SLP_S3_L, PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(SLP_SUS_L, PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(SYS_SLP_S0IX_L, PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(TABLET_MODE_L, PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr) +GPIO_INT(USB_C0_BC12_INT_ODL, PIN(C, 6), GPIO_INT_BOTH, bc12_interrupt) +GPIO_INT(USB_C0_C2_TCPC_INT_ODL, PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event) +GPIO_INT(USB_C0_PPC_INT_ODL, PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt) +GPIO_INT(USB_C0_RT_INT_ODL, PIN(B, 1), GPIO_INT_BOTH, retimer_interrupt) +GPIO_INT(USB_C1_BC12_INT_ODL, PIN(5, 0), GPIO_INT_BOTH, bc12_interrupt) +GPIO_INT(USB_C1_PPC_INT_ODL, PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt) +GPIO_INT(USB_C1_RT_INT_ODL, PIN(A, 0), GPIO_INT_BOTH, retimer_interrupt) +GPIO_INT(USB_C1_TCPC_INT_ODL, PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event) +GPIO_INT(USB_C2_BC12_INT_ODL, PIN(8, 3), GPIO_INT_BOTH, bc12_interrupt) +GPIO_INT(USB_C2_PPC_INT_ODL, PIN(7, 0), GPIO_INT_BOTH, ppc_interrupt) +GPIO_INT(USB_C2_RT_INT_ODL, PIN(4, 1), GPIO_INT_BOTH, retimer_interrupt) + +/* USED GPIOs: */ +GPIO(CCD_MODE_ODL, PIN(E, 5), GPIO_INPUT) +GPIO(CHARGER_VAP_OTG_EN, PIN(7, 3), GPIO_OUT_LOW) +GPIO(CPU_C10_GATE_L, PIN(6, 7), GPIO_INPUT) +GPIO(EC_BATT_PRES_ODL, PIN(A, 3), GPIO_INPUT) +GPIO(EC_ENTERING_RW, PIN(0, 3), GPIO_OUT_LOW) +GPIO(EC_EN_EDP_BL, PIN(D, 3), GPIO_OUT_HIGH) +GPIO(EC_GSC_PACKET_MODE, PIN(7, 5), GPIO_OUT_LOW) +GPIO(EC_I2C_BAT_SCL, PIN(3, 3), GPIO_INPUT) +GPIO(EC_I2C_BAT_SDA, PIN(3, 6), GPIO_INPUT) +GPIO(EC_I2C_MISC_SCL_R, PIN(B, 3), GPIO_INPUT) +GPIO(EC_I2C_MISC_SDA_R, PIN(B, 2), GPIO_INPUT) +GPIO(EC_I2C_SENSOR_SCL, PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V) +GPIO(EC_I2C_SENSOR_SDA, PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V) +GPIO(EC_I2C_USB_C0_C2_PPC_BC_SCL, PIN(9, 2), GPIO_INPUT) +GPIO(EC_I2C_USB_C0_C2_PPC_BC_SDA, PIN(9, 1), GPIO_INPUT) +GPIO(EC_I2C_USB_C0_C2_RT_SCL, PIN(D, 1), GPIO_INPUT) +GPIO(EC_I2C_USB_C0_C2_RT_SDA, PIN(D, 0), GPIO_INPUT) +GPIO(EC_I2C_USB_C0_C2_TCPC_SCL, PIN(9, 0), GPIO_INPUT) +GPIO(EC_I2C_USB_C0_C2_TCPC_SDA, PIN(8, 7), GPIO_INPUT) +GPIO(EC_I2C_USB_C1_MIX_SCL, PIN(E, 4), GPIO_INPUT) +GPIO(EC_I2C_USB_C1_MIX_SDA, PIN(E, 3), GPIO_INPUT) +GPIO(EC_I2C_USB_C1_TCPC_SCL, PIN(F, 3), GPIO_INPUT) +GPIO(EC_I2C_USB_C1_TCPC_SDA, PIN(F, 2), GPIO_INPUT) +GPIO(EC_KB_BL_EN_L, PIN(8, 6), GPIO_OUT_HIGH) +GPIO(EC_PCHHOT_ODL, PIN(7, 4), GPIO_INPUT) +GPIO(EC_PCH_INT_ODL, PIN(B, 0), GPIO_ODR_HIGH) +GPIO(EC_PCH_PWR_BTN_ODL, PIN(C, 1), GPIO_ODR_HIGH) +GPIO(EC_PCH_RSMRST_L, PIN(A, 6), GPIO_OUT_LOW) +GPIO(EC_PCH_RTCRST, PIN(7, 6), GPIO_OUT_LOW) +GPIO(EC_PCH_SYS_PWROK, PIN(3, 7), GPIO_OUT_LOW) +GPIO(EC_PCH_WAKE_R_ODL, PIN(C, 0), GPIO_INPUT) +GPIO(EC_PROCHOT_ODL, PIN(6, 3), GPIO_ODR_HIGH) +GPIO(EN_PP5000_FAN, PIN(6, 1), GPIO_OUT_HIGH) +GPIO(EN_PP5000_USBA_R, PIN(D, 7), GPIO_OUT_LOW) +GPIO(EN_S5_RAILS, PIN(B, 6), GPIO_OUT_LOW) +GPIO(IMVP9_VRRDY_OD, PIN(4, 3), GPIO_INPUT) +GPIO(PCH_PWROK, PIN(7, 2), GPIO_OUT_LOW) +GPIO(SYS_RST_ODL, PIN(C, 5), GPIO_ODR_HIGH) +GPIO(USB_C0_C2_TCPC_RST_ODL, PIN(A, 7), GPIO_OUT_LOW) +GPIO(USB_C1_FRS_EN, PIN(9, 4), GPIO_OUT_LOW) +GPIO(USB_C1_RST_ODL, PIN(9, 6), GPIO_ODR_LOW) +GPIO(USB_C1_RT_RST_R_ODL, PIN(0, 2), GPIO_ODR_LOW) +GPIO(VCCST_PWRGD_OD, PIN(A, 4), GPIO_ODR_LOW) + +/* UART alternate functions */ +ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0) /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */ + +/* I2C alternate functions */ +ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0) /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */ +ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0) /* GPIO87/I2C1_SDA0 */ +ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0) /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */ +ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0) /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */ +ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V) /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */ +ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0) /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */ +ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0) /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */ +ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0) /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */ + +/* PWM alternate functions */ +ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0) /* GPIO40/TA1 */ +ALTERNATE(PIN_MASK(6, 0x01), 0, MODULE_PWM, 0) /* GPIO60/PWM7 */ +ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0) /* GPIO80/PWM3 */ +ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0) /* GPIOB7/PWM5 */ +ALTERNATE(PIN_MASK(C, 0x1c), 0, MODULE_PWM, 0) /* GPIOC4/PWM2, GPIOC3/PWM0, GPIOC2/PWM1/I2C6_SCL0 */ + +/* ADC alternate functions */ +ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0) /* GPIO34/PS2_DAT2/ADC6 */ +ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0) /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */ +ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0) /* GPIOE1/ADC7 */ + +/* KB alternate functions */ +ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH) /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */ +ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH) /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */ +ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */ +ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH) /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */ +ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */ +ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH) /* KSO14/GPIO82 */ + +/* PMU alternate functions */ +ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */ +ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */ +ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */ + +/* Unused Pins */ +UNUSED(PIN(D, 6)) /* GPOD6/CR_SOUT3/SHDF_ESPI_L */ +UNUSED(PIN(3, 2)) /* GPO32/TRIS_L */ +UNUSED(PIN(3, 5)) /* GPO35/CR_SOUT4/TEST_L */ +UNUSED(PIN(6, 6)) /* GPO66/ARM_L_x86 */ + +/* Pre-configured PSL balls: J8 K6 */ + + +/* + * The NPCX keyboard driver does not use named GPIOs to access + * keyboard scan pins, so we do not list them in *gpio.inc. However, when + * KEYBOARD_COL2_INVERTED is defined, this name is required. + */ +GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW) + +/* + * GPIOE1 is an ALT function ADC INPUT on board ID 2 and a GPIO INPUT on + * board ID 1. This declaration gives us a signal name to use on board + * ID 1. + */ +GPIO(ID_1_EC_BATT_PRES_ODL, PIN(E, 1), GPIO_INPUT) + +/* + * GPIO34 is an INPUT on board ID 2 and ODR_LOW on board ID 1. + * + * Since this pin is pulled up to 3.3V through a 30.9K ohm resistor on + * board ID 2, we will leak about 0.3mW until the pin is put in ALT mode + * when MODULE_ADC configuration runs. Initializing the pin to ODR_LOW + * gives us full control on both boards. + */ +GPIO(ID_1_USB_C0_C2_TCPC_RST_ODL, PIN(3, 4), GPIO_ODR_LOW) + +IOEX(ID_1_USB_C0_RT_RST_ODL, EXPIN(IOEX_C0_NCT38XX, 0, 2), GPIO_ODR_LOW) +IOEX(USB_C0_FRS_EN, EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_LOW) +IOEX(USB_C0_OC_ODL, EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_ODR_HIGH) +IOEX(USB_C0_RT_RST_ODL, EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW) + +IOEX(USB_C2_RT_RST_ODL, EXPIN(IOEX_C2_NCT38XX, 0, 2), GPIO_ODR_LOW) +IOEX(USB_C2_FRS_EN, EXPIN(IOEX_C2_NCT38XX, 0, 4), GPIO_LOW) +IOEX(USB_C1_OC_ODL, EXPIN(IOEX_C2_NCT38XX, 0, 6), GPIO_ODR_HIGH) +IOEX(USB_C2_OC_ODL, EXPIN(IOEX_C2_NCT38XX, 0, 7), GPIO_ODR_HIGH) diff --git a/board/gimble/i2c.c b/board/gimble/i2c.c new file mode 100644 index 0000000000..02890a3a16 --- /dev/null +++ b/board/gimble/i2c.c @@ -0,0 +1,77 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" + +#include "i2c.h" + +/* I2C port map configuration */ +const struct i2c_port_t i2c_ports[] = { + { + /* I2C0 */ + .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_EC_I2C_SENSOR_SCL, + .sda = GPIO_EC_I2C_SENSOR_SDA, + }, + { + /* I2C1 */ + .name = "tcpc0,2", + .port = I2C_PORT_USB_C0_C2_TCPC, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C0_C2_TCPC_SCL, + .sda = GPIO_EC_I2C_USB_C0_C2_TCPC_SDA, + }, + { + /* I2C2 */ + .name = "ppc0,2", + .port = I2C_PORT_USB_C0_C2_PPC, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SCL, + .sda = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SDA, + }, + { + /* I2C3 */ + .name = "retimer0,2", + .port = I2C_PORT_USB_C0_C2_MUX, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C0_C2_RT_SCL, + .sda = GPIO_EC_I2C_USB_C0_C2_RT_SDA, + }, + { + /* I2C4 C1 TCPC */ + .name = "tcpc1", + .port = I2C_PORT_USB_C1_TCPC, + .kbps = 400, + .scl = GPIO_EC_I2C_USB_C1_TCPC_SCL, + .sda = GPIO_EC_I2C_USB_C1_TCPC_SDA, + }, + { + /* I2C5 */ + .name = "battery", + .port = I2C_PORT_BATTERY, + .kbps = 100, + .scl = GPIO_EC_I2C_BAT_SCL, + .sda = GPIO_EC_I2C_BAT_SDA, + }, + { + /* I2C6 */ + .name = "ppc1", + .port = I2C_PORT_USB_C1_PPC, + .kbps = 400, + .scl = GPIO_EC_I2C_USB_C1_MIX_SCL, + .sda = GPIO_EC_I2C_USB_C1_MIX_SDA, + }, + { + /* I2C7 */ + .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_EC_I2C_MISC_SCL_R, + .sda = GPIO_EC_I2C_MISC_SDA_R, + }, +}; +const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); diff --git a/board/gimble/keyboard.c b/board/gimble/keyboard.c new file mode 100644 index 0000000000..b2f1c9f10c --- /dev/null +++ b/board/gimble/keyboard.c @@ -0,0 +1,25 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" + +#include "keyboard_scan.h" +#include "timer.h" + +/* Keyboard scan setting */ +struct keyboard_scan_config keyscan_config = { + /* Increase from 50 us, because KSO_02 passes through the H1. */ + .output_settle_us = 80, + /* Other values should be the same as the default configuration. */ + .debounce_down_us = 9 * MSEC, + .debounce_up_us = 30 * MSEC, + .scan_period_us = 3 * MSEC, + .min_post_scan_delay_us = 1000, + .poll_timeout_us = 100 * MSEC, + .actual_key_mask = { + 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, + 0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca /* full set */ + }, +}; diff --git a/board/gimble/led.c b/board/gimble/led.c new file mode 100644 index 0000000000..aa8da52778 --- /dev/null +++ b/board/gimble/led.c @@ -0,0 +1,90 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Brya specific PWM LED settings: there are 2 LEDs on each side of the board, + * each one can be controlled separately. The LED colors are white or amber, + * and the default behavior is tied to the charging process: both sides are + * amber while charging the battery and white when the battery is charged. + */ + +#include "common.h" +#include "ec_commands.h" +#include "led_pwm.h" +#include "pwm.h" +#include "util.h" + +const enum ec_led_id supported_led_ids[] = { + EC_LED_ID_LEFT_LED, + EC_LED_ID_RIGHT_LED, +}; + +const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); + +/* + * We only have a white and an amber LED, so setting any other color results in + * both LEDs being off. + */ +struct pwm_led led_color_map[EC_LED_COLOR_COUNT] = { + /* Amber, White */ + [EC_LED_COLOR_RED] = { 0, 0 }, + [EC_LED_COLOR_GREEN] = { 0, 0 }, + [EC_LED_COLOR_BLUE] = { 0, 0 }, + [EC_LED_COLOR_YELLOW] = { 0, 0 }, + [EC_LED_COLOR_WHITE] = { 0, 100 }, + [EC_LED_COLOR_AMBER] = { 100, 0 }, +}; + +/* Two logical LEDs with amber and white channels. */ +struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = { + { + .ch0 = PWM_CH_LED1, + .ch1 = PWM_CH_LED2, + .ch2 = PWM_LED_NO_CHANNEL, + .enable = &pwm_enable, + .set_duty = &pwm_set_duty, + }, + { + .ch0 = PWM_CH_LED3, + .ch1 = PWM_CH_LED4, + .ch2 = PWM_LED_NO_CHANNEL, + .enable = &pwm_enable, + .set_duty = &pwm_set_duty, + }, +}; + +void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) +{ + memset(brightness_range, '\0', + sizeof(*brightness_range) * EC_LED_COLOR_COUNT); + brightness_range[EC_LED_COLOR_AMBER] = 100; + brightness_range[EC_LED_COLOR_WHITE] = 100; +} + +int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) +{ + enum pwm_led_id pwm_id; + + /* Convert ec_led_id to pwm_led_id. */ + switch (led_id) { + case EC_LED_ID_LEFT_LED: + pwm_id = PWM_LED0; + break; + case EC_LED_ID_RIGHT_LED: + pwm_id = PWM_LED1; + break; + default: + return EC_ERROR_UNKNOWN; + } + + if (brightness[EC_LED_COLOR_WHITE]) + set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE); + else if (brightness[EC_LED_COLOR_AMBER]) + set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER); + else + /* Otherwise, the "color" is "off". */ + set_pwm_led_color(pwm_id, -1); + + return EC_SUCCESS; +} diff --git a/board/gimble/pwm.c b/board/gimble/pwm.c new file mode 100644 index 0000000000..a6b65b038c --- /dev/null +++ b/board/gimble/pwm.c @@ -0,0 +1,70 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" +#include "hooks.h" + +#include "pwm.h" +#include "pwm_chip.h" + +const struct pwm_t pwm_channels[] = { + [PWM_CH_LED2] = { + .channel = 0, + .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, + .freq = 4800, + }, + [PWM_CH_LED3] = { + .channel = 1, + .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, + .freq = 4800, + }, + [PWM_CH_LED1] = { + .channel = 2, + .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, + .freq = 4800, + }, + [PWM_CH_KBLIGHT] = { + .channel = 3, + .flags = 0, + /* + * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent + * flicker. Higher frequencies consume similar average power to + * lower PWM frequencies, but higher frequencies record a much + * lower maximum power. + */ + .freq = 2400, + }, + [PWM_CH_FAN] = { + .channel = 5, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 + }, + [PWM_CH_LED4] = { + .channel = 7, + .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, + .freq = 4800, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); + +static void board_pwm_init(void) +{ + /* + * Turn on all the LED at 50%. + * Turn on the fan at 100%. + */ + pwm_enable(PWM_CH_LED1, 1); + pwm_set_duty(PWM_CH_LED1, 50); + pwm_enable(PWM_CH_LED2, 1); + pwm_set_duty(PWM_CH_LED2, 50); + pwm_enable(PWM_CH_LED3, 1); + pwm_set_duty(PWM_CH_LED3, 50); + pwm_enable(PWM_CH_LED4, 1); + pwm_set_duty(PWM_CH_LED4, 50); + + pwm_enable(PWM_CH_KBLIGHT, 1); + pwm_set_duty(PWM_CH_KBLIGHT, 50); +} +DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT); diff --git a/board/gimble/sensors.c b/board/gimble/sensors.c new file mode 100644 index 0000000000..434553f5dd --- /dev/null +++ b/board/gimble/sensors.c @@ -0,0 +1,321 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" +#include "accelgyro.h" +#include "adc_chip.h" +#include "driver/accel_lis2dw12.h" +#include "driver/accelgyro_lsm6dso.h" +#include "driver/als_tcs3400_public.h" +#include "hooks.h" +#include "motion_sense.h" +#include "temp_sensor.h" +#include "thermal.h" +#include "temp_sensor/thermistor.h" + +/* ADC configuration */ +const struct adc_t adc_channels[] = { + [ADC_TEMP_SENSOR_1_DDR_SOC] = { + .name = "TEMP_DDR_SOC", + .input_ch = NPCX_ADC_CH0, + .factor_mul = ADC_MAX_VOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + }, + [ADC_TEMP_SENSOR_2_CHARGER] = { + .name = "TEMP_CHARGER", + .input_ch = NPCX_ADC_CH1, + .factor_mul = ADC_MAX_VOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); + +K_MUTEX_DEFINE(g_lid_accel_mutex); +K_MUTEX_DEFINE(g_base_accel_mutex); +static struct stprivate_data g_lis2dw12_data; +static struct lsm6dso_data lsm6dso_data; + +/* TODO(b/184779333): calibrate the orientation matrix on later board stage */ +static const mat33_fp_t lid_standard_ref = { + { 0, FLOAT_TO_FP(1), 0}, + { FLOAT_TO_FP(1), 0, 0}, + { 0, 0, FLOAT_TO_FP(-1)} +}; + +/* TODO(b/184779743): verify orientation matrix */ +static const mat33_fp_t base_standard_ref = { + { FLOAT_TO_FP(1), 0, 0}, + { 0, FLOAT_TO_FP(-1), 0}, + { 0, 0, FLOAT_TO_FP(-1)} +}; + +/* TCS3400 private data */ +static struct als_drv_data_t g_tcs3400_data = { + .als_cal.scale = 1, + .als_cal.uscale = 0, + .als_cal.offset = 0, + .als_cal.channel_scale = { + .k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc from VPD */ + .cover_scale = ALS_CHANNEL_SCALE(1.0), /* CT */ + }, +}; + +/* + * TODO: b/184702900 need to calibrate ALS/RGB sensor. At default settings, + * shining phone flashlight on sensor pegs all readings at 0xFFFF. + */ +static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = { + .calibration.rgb_cal[X] = { + .offset = 0, + .coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0), + .coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0), + .coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0), + .coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0), + .scale = { + .k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */ + .cover_scale = ALS_CHANNEL_SCALE(1.0) + } + }, + .calibration.rgb_cal[Y] = { + .offset = 0, + .coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0), + .coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0), + .coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0), + .coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0), + .scale = { + .k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */ + .cover_scale = ALS_CHANNEL_SCALE(1.0) + }, + }, + .calibration.rgb_cal[Z] = { + .offset = 0, + .coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0), + .coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0), + .coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0), + .coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0), + .scale = { + .k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */ + .cover_scale = ALS_CHANNEL_SCALE(1.0) + } + }, + .calibration.irt = INT_TO_FP(1), + .saturation.again = TCS_DEFAULT_AGAIN, + .saturation.atime = TCS_DEFAULT_ATIME, +}; + +struct motion_sensor_t motion_sensors[] = { + [LID_ACCEL] = { + .name = "Lid Accel", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_LIS2DW12, + .type = MOTIONSENSE_TYPE_ACCEL, + .location = MOTIONSENSE_LOC_LID, + .drv = &lis2dw12_drv, + .mutex = &g_lid_accel_mutex, + .drv_data = &g_lis2dw12_data, + .int_signal = GPIO_EC_ACCEL_INT_R_L, + .port = I2C_PORT_SENSOR, + .i2c_spi_addr_flags = LIS2DW12_ADDR0, + .flags = MOTIONSENSE_FLAG_INT_SIGNAL, + .rot_standard_ref = &lid_standard_ref, /* identity matrix */ + .default_range = 2, /* g */ + .min_frequency = LIS2DW12_ODR_MIN_VAL, + .max_frequency = LIS2DW12_ODR_MAX_VAL, + .config = { + /* EC use accel for angle detection */ + [SENSOR_CONFIG_EC_S0] = { + .odr = 12500 | ROUND_UP_FLAG, + }, + /* Sensor on for lid angle detection */ + [SENSOR_CONFIG_EC_S3] = { + .odr = 10000 | ROUND_UP_FLAG, + }, + }, + }, + + [BASE_ACCEL] = { + .name = "Base Accel", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_LSM6DSO, + .type = MOTIONSENSE_TYPE_ACCEL, + .location = MOTIONSENSE_LOC_BASE, + .drv = &lsm6dso_drv, + .mutex = &g_base_accel_mutex, + .drv_data = &lsm6dso_data, + .int_signal = GPIO_EC_IMU_INT_R_L, + .flags = MOTIONSENSE_FLAG_INT_SIGNAL, + .port = I2C_PORT_SENSOR, + .i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS, + .rot_standard_ref = &base_standard_ref, + .default_range = 4, /* g */ + .min_frequency = LSM6DSO_ODR_MIN_VAL, + .max_frequency = LSM6DSO_ODR_MAX_VAL, + .config = { + [SENSOR_CONFIG_EC_S0] = { + .odr = 13000 | ROUND_UP_FLAG, + .ec_rate = 100 * MSEC, + }, + [SENSOR_CONFIG_EC_S3] = { + .odr = 10000 | ROUND_UP_FLAG, + .ec_rate = 100 * MSEC, + }, + }, + }, + + [BASE_GYRO] = { + .name = "Base Gyro", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_LSM6DSO, + .type = MOTIONSENSE_TYPE_GYRO, + .location = MOTIONSENSE_LOC_BASE, + .drv = &lsm6dso_drv, + .mutex = &g_base_accel_mutex, + .drv_data = &lsm6dso_data, + .int_signal = GPIO_EC_IMU_INT_R_L, + .flags = MOTIONSENSE_FLAG_INT_SIGNAL, + .port = I2C_PORT_SENSOR, + .i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS, + .default_range = 1000 | ROUND_UP_FLAG, /* dps */ + .rot_standard_ref = &base_standard_ref, + .min_frequency = LSM6DSO_ODR_MIN_VAL, + .max_frequency = LSM6DSO_ODR_MAX_VAL, + .config = { + [SENSOR_CONFIG_EC_S0] = { + .odr = 13000 | ROUND_UP_FLAG, + .ec_rate = 100 * MSEC, + }, + [SENSOR_CONFIG_EC_S3] = { + .odr = 10000 | ROUND_UP_FLAG, + .ec_rate = 100 * MSEC, + }, + }, + }, + + [CLEAR_ALS] = { + .name = "Clear Light", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_TCS3400, + .type = MOTIONSENSE_TYPE_LIGHT, + .location = MOTIONSENSE_LOC_CAMERA, + .drv = &tcs3400_drv, + .drv_data = &g_tcs3400_data, + .port = I2C_PORT_SENSOR, + .i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS, + .rot_standard_ref = NULL, + .default_range = 0x10000, /* scale = 1x, uscale = 0 */ + .min_frequency = TCS3400_LIGHT_MIN_FREQ, + .max_frequency = TCS3400_LIGHT_MAX_FREQ, + .config = { + /* Run ALS sensor in S0 */ + [SENSOR_CONFIG_EC_S0] = { + .odr = 1000, + }, + }, + }, + + [RGB_ALS] = { + /* + * RGB channels read by CLEAR_ALS and so the i2c port and + * address do not need to be defined for RGB_ALS. + */ + .name = "RGB Light", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_TCS3400, + .type = MOTIONSENSE_TYPE_LIGHT_RGB, + .location = MOTIONSENSE_LOC_CAMERA, + .drv = &tcs3400_rgb_drv, + .drv_data = &g_tcs3400_rgb_data, + .rot_standard_ref = NULL, + .default_range = 0x10000, /* scale = 1x, uscale = 0 */ + }, +}; +const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); + +/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */ +const struct motion_sensor_t *motion_als_sensors[] = { + &motion_sensors[CLEAR_ALS], +}; +BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT); + +static void baseboard_sensors_init(void) +{ + /* Enable gpio interrupt for lid accel sensor */ + gpio_enable_interrupt(GPIO_EC_ACCEL_INT_R_L); + /* Enable interrupt for the TCS3400 color light sensor */ + gpio_enable_interrupt(GPIO_EC_ALS_RGB_INT_R_L); + /* Enable gpio interrupt for base accelgyro sensor */ + gpio_enable_interrupt(GPIO_EC_IMU_INT_R_L); +} +DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1); + +/* Temperature sensor configuration */ +const struct temp_sensor_t temp_sensors[] = { + [TEMP_SENSOR_1_DDR_SOC] = { + .name = "DDR and SOC", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1_DDR_SOC + }, + [TEMP_SENSOR_2_CHARGER] = { + .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2_CHARGER + }, +}; +BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); + +/* + * TODO(b/180681346): update for Alder Lake/brya + * + * Tiger Lake specifies 100 C as maximum TDP temperature. THRMTRIP# occurs at + * 130 C. However, sensor is located next to DDR, so we need to use the lower + * DDR temperature limit (85 C) + */ +static const struct ec_thermal_config thermal_cpu = { + .temp_host = { + [EC_TEMP_THRESH_HIGH] = C_TO_K(70), + [EC_TEMP_THRESH_HALT] = C_TO_K(80), + }, + .temp_host_release = { + [EC_TEMP_THRESH_HIGH] = C_TO_K(65), + }, + .temp_fan_off = C_TO_K(35), + .temp_fan_max = C_TO_K(50), +}; + +/* + * TODO(b/180681346): update for Alder Lake/brya + * + * Inductor limits - used for both charger and PP3300 regulator + * + * Need to use the lower of the charger IC, PP3300 regulator, and the inductors + * + * Charger max recommended temperature 100C, max absolute temperature 125C + * PP3300 regulator: operating range -40 C to 145 C + * + * Inductors: limit of 125c + * PCB: limit is 80c + */ +static const struct ec_thermal_config thermal_inductor = { + .temp_host = { + [EC_TEMP_THRESH_HIGH] = C_TO_K(75), + [EC_TEMP_THRESH_HALT] = C_TO_K(80), + }, + .temp_host_release = { + [EC_TEMP_THRESH_HIGH] = C_TO_K(65), + }, + .temp_fan_off = C_TO_K(40), + .temp_fan_max = C_TO_K(55), +}; + +/* this should really be "const" */ +struct ec_thermal_config thermal_params[] = { + [TEMP_SENSOR_1_DDR_SOC] = thermal_cpu, + [TEMP_SENSOR_2_CHARGER] = thermal_inductor, +}; +BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT); diff --git a/board/gimble/tune_mp2964.c b/board/gimble/tune_mp2964.c new file mode 100644 index 0000000000..c95f06d7fd --- /dev/null +++ b/board/gimble/tune_mp2964.c @@ -0,0 +1,41 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Tune the MP2964 IMVP9.1 parameters for brya */ + +#include "console.h" +#include "hooks.h" +#include "mp2964.h" + +const static struct mp2964_reg_val rail_a[] = { + { MP2964_MFR_ALT_SET, 0xe081 }, /* ALERT_DELAY = 200ns */ +}; +const static struct mp2964_reg_val rail_b[] = { + { MP2964_MFR_ALT_SET, 0xe081 }, /* ALERT_DELAY = 200ns */ +}; + +static void mp2964_on_startup(void) +{ + static int chip_updated; + int status; + + if (get_board_id() != 1) + return; + + if (chip_updated) + return; + + chip_updated = 1; + + ccprintf("%s: attempting to tune PMIC\n", __func__); + + status = mp2964_tune(rail_a, ARRAY_SIZE(rail_a), + rail_b, ARRAY_SIZE(rail_b)); + if (status != EC_SUCCESS) + ccprintf("%s: could not update all settings\n", __func__); +} + +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, mp2964_on_startup, + HOOK_PRIO_FIRST); diff --git a/board/gimble/usbc_config.c b/board/gimble/usbc_config.c new file mode 100644 index 0000000000..f6aa7af363 --- /dev/null +++ b/board/gimble/usbc_config.c @@ -0,0 +1,389 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" + +#include "driver/bc12/pi3usb9201_public.h" +#include "driver/ppc/nx20p348x.h" +#include "driver/ppc/syv682x_public.h" +#include "driver/retimer/bb_retimer_public.h" +#include "driver/tcpm/nct38xx.h" +#include "driver/tcpm/ps8xxx_public.h" +#include "driver/tcpm/tcpci.h" +#include "fw_config.h" +#include "hooks.h" +#include "ioexpander.h" +#include "system.h" +#include "timer.h" +#include "usbc_config.h" +#include "usbc_ppc.h" +#include "usb_mux.h" +#include "usb_pd_tcpm.h" + +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) + +/* USBC TCPC configuration */ +const struct tcpc_config_t tcpc_config[] = { + [USBC_PORT_C0] = { + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C0_C2_TCPC, + .addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS, + }, + .drv = &nct38xx_tcpm_drv, + .flags = TCPC_FLAGS_TCPCI_REV2_0, + }, + [USBC_PORT_C1] = { + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C1_TCPC, + .addr_flags = PS8751_I2C_ADDR1_FLAGS, + }, + .drv = &ps8xxx_tcpm_drv, + .flags = TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V, + }, + [USBC_PORT_C2] = { + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C0_C2_TCPC, + .addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS, + }, + .drv = &nct38xx_tcpm_drv, + .flags = TCPC_FLAGS_TCPCI_REV2_0, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT); +BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT); + +/* USBC PPC configuration */ +struct ppc_config_t ppc_chips[] = { + [USBC_PORT_C0] = { + .i2c_port = I2C_PORT_USB_C0_C2_PPC, + .i2c_addr_flags = SYV682X_ADDR0_FLAGS, + .drv = &syv682x_drv, + }, + [USBC_PORT_C1] = { + /* Compatible with Silicon Mitus SM536A0 */ + .i2c_port = I2C_PORT_USB_C1_PPC, + .i2c_addr_flags = NX20P3483_ADDR2_FLAGS, + .drv = &nx20p348x_drv, + }, + [USBC_PORT_C2] = { + .i2c_port = I2C_PORT_USB_C0_C2_PPC, + /* + * b/179987870 + * schematics I2C map says ADDR3 + */ + .i2c_addr_flags = SYV682X_ADDR2_FLAGS, + .drv = &syv682x_drv, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT); + +unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); + +/* USBC mux configuration - Alder Lake includes internal mux */ +static const struct usb_mux usbc0_tcss_usb_mux = { + .usb_port = USBC_PORT_C0, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, +}; +static const struct usb_mux usbc2_tcss_usb_mux = { + .usb_port = USBC_PORT_C2, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, +}; + +/* + * USB3 DB mux configuration - the top level mux still needs to be set + * to the virtual_usb_mux_driver so the AP gets notified of mux changes + * and updates the TCSS configuration on state changes. + */ +static const struct usb_mux usbc1_usb3_db_retimer = { + .usb_port = USBC_PORT_C1, + .driver = &tcpci_tcpm_usb_mux_driver, + .hpd_update = &ps8xxx_tcpc_update_hpd_status, +}; + +const struct usb_mux usb_muxes[] = { + [USBC_PORT_C0] = { + .usb_port = USBC_PORT_C0, + .driver = &bb_usb_retimer, + .i2c_port = I2C_PORT_USB_C0_C2_MUX, + .i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR, + .next_mux = &usbc0_tcss_usb_mux, + }, + [USBC_PORT_C1] = { + /* PS8815 DB */ + .usb_port = USBC_PORT_C1, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, + .next_mux = &usbc1_usb3_db_retimer, + }, + [USBC_PORT_C2] = { + .usb_port = USBC_PORT_C2, + .driver = &bb_usb_retimer, + .i2c_port = I2C_PORT_USB_C0_C2_MUX, + .i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR, + .next_mux = &usbc2_tcss_usb_mux, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT); + +/* BC1.2 charger detect configuration */ +const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = { + [USBC_PORT_C0] = { + .i2c_port = I2C_PORT_USB_C0_C2_BC12, + .i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS, + }, + [USBC_PORT_C1] = { + .i2c_port = I2C_PORT_USB_C1_BC12, + .i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS, + }, + [USBC_PORT_C2] = { + .i2c_port = I2C_PORT_USB_C0_C2_BC12, + .i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT); + +/* + * USB C0 and C2 uses burnside bridge chips and have their reset + * controlled by their respective TCPC chips acting as GPIO expanders. + * + * ioex_init() is normally called before we take the TCPCs out of + * reset, so we need to start in disabled mode, then explicitly + * call ioex_init(). + */ + +struct ioexpander_config_t ioex_config[] = { + [IOEX_C0_NCT38XX] = { + .i2c_host_port = I2C_PORT_USB_C0_C2_TCPC, + .i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS, + .drv = &nct38xx_ioexpander_drv, + .flags = IOEX_FLAGS_DISABLED, + }, + [IOEX_C2_NCT38XX] = { + .i2c_host_port = I2C_PORT_USB_C0_C2_TCPC, + .i2c_addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS, + .drv = &nct38xx_ioexpander_drv, + .flags = IOEX_FLAGS_DISABLED, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT); + +void config_usb_db_type(void) +{ + enum ec_cfg_usb_db_type db_type = ec_cfg_usb_db_type(); + + /* + * TODO(b/180434685): implement multiple DB types + */ + + CPRINTS("Configured USB DB type number is %d", db_type); +} + +__override int bb_retimer_power_handle(const struct usb_mux *me, int on_off) +{ + enum ioex_signal rst_signal; + + if (me->usb_port == USBC_PORT_C0) { + if (get_board_id() == 1) + rst_signal = IOEX_ID_1_USB_C0_RT_RST_ODL; + else + rst_signal = IOEX_USB_C0_RT_RST_ODL; + } else if (me->usb_port == USBC_PORT_C2) { + rst_signal = IOEX_USB_C2_RT_RST_ODL; + } else { + return EC_ERROR_INVAL; + } + + /* + * We do not have a load switch for the burnside bridge chips, + * so we only need to sequence reset. + */ + + if (on_off) { + /* + * Tpw, minimum time from VCC to RESET_N de-assertion is 100us. + * For boards that don't provide a load switch control, the + * retimer_init() function ensures power is up before calling + * this function. + */ + ioex_set_level(rst_signal, 1); + /* + * Allow 1ms time for the retimer to power up lc_domain + * which powers I2C controller within retimer + */ + msleep(1); + } else { + ioex_set_level(rst_signal, 0); + msleep(1); + } + return EC_SUCCESS; +} + +void board_reset_pd_mcu(void) +{ + enum gpio_signal tcpc_rst; + + if (get_board_id() == 1) + tcpc_rst = GPIO_ID_1_USB_C0_C2_TCPC_RST_ODL; + else + tcpc_rst = GPIO_USB_C0_C2_TCPC_RST_ODL; + + /* + * TODO(b/179648104): figure out correct timing + */ + + gpio_set_level(tcpc_rst, 0); + if (ec_cfg_usb_db_type() != DB_USB_ABSENT) { + gpio_set_level(GPIO_USB_C1_RST_ODL, 0); + gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 0); + } + + /* + * delay for power-on to reset-off and min. assertion time + */ + + msleep(20); + + gpio_set_level(tcpc_rst, 1); + if (ec_cfg_usb_db_type() != DB_USB_ABSENT) { + gpio_set_level(GPIO_USB_C1_RST_ODL, 1); + gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1); + } + + /* wait for chips to come up */ + + msleep(50); +} + +static void board_tcpc_init(void) +{ + int i; + + /* Don't reset TCPCs after initial reset */ + if (!system_jumped_late()) { + board_reset_pd_mcu(); + + for (i = 0; i < CONFIG_IO_EXPANDER_PORT_COUNT; ++i) { + ioex_config[i].flags &= ~IOEX_FLAGS_DISABLED; + ioex_init(i); + } + } + + /* Enable PPC interrupts. */ + gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL); + gpio_enable_interrupt(GPIO_USB_C2_PPC_INT_ODL); + + /* Enable TCPC interrupts. */ + gpio_enable_interrupt(GPIO_USB_C0_C2_TCPC_INT_ODL); + + /* Enable BC1.2 interrupts. */ + gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL); + gpio_enable_interrupt(GPIO_USB_C2_BC12_INT_ODL); + + if (ec_cfg_usb_db_type() != DB_USB_ABSENT) { + gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL); + gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL); + gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL); + } +} +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET); + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + + if (gpio_get_level(GPIO_USB_C0_C2_TCPC_INT_ODL) == 0) + status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_2; + + if ((ec_cfg_usb_db_type() != DB_USB_ABSENT) && + gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0) + status |= PD_STATUS_TCPC_ALERT_1; + + return status; +} + +int ppc_get_alert_status(int port) +{ + if (port == USBC_PORT_C0) + return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0; + else if ((port == USBC_PORT_C1) && + (ec_cfg_usb_db_type() != DB_USB_ABSENT)) + return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0; + else if (port == USBC_PORT_C2) + return gpio_get_level(GPIO_USB_C2_PPC_INT_ODL) == 0; + return 0; +} + +void tcpc_alert_event(enum gpio_signal signal) +{ + switch (signal) { + case GPIO_USB_C0_C2_TCPC_INT_ODL: + schedule_deferred_pd_interrupt(USBC_PORT_C0); + break; + case GPIO_USB_C1_TCPC_INT_ODL: + if (ec_cfg_usb_db_type() == DB_USB_ABSENT) + break; + schedule_deferred_pd_interrupt(USBC_PORT_C1); + break; + default: + break; + } +} + +void bc12_interrupt(enum gpio_signal signal) +{ + switch (signal) { + case GPIO_USB_C0_BC12_INT_ODL: + task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12); + break; + case GPIO_USB_C1_BC12_INT_ODL: + if (ec_cfg_usb_db_type() == DB_USB_ABSENT) + break; + task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12); + break; + case GPIO_USB_C2_BC12_INT_ODL: + task_set_event(TASK_ID_USB_CHG_P2, USB_CHG_EVENT_BC12); + break; + default: + break; + } +} + +void ppc_interrupt(enum gpio_signal signal) +{ + switch (signal) { + case GPIO_USB_C0_PPC_INT_ODL: + syv682x_interrupt(USBC_PORT_C0); + break; + case GPIO_USB_C1_PPC_INT_ODL: + switch (ec_cfg_usb_db_type()) { + case DB_USB_ABSENT: + case DB_USB_ABSENT2: + break; + case DB_USB3_PS8815: + nx20p348x_interrupt(USBC_PORT_C1); + break; + } + break; + case GPIO_USB_C2_PPC_INT_ODL: + syv682x_interrupt(USBC_PORT_C2); + break; + default: + break; + } +} + +void retimer_interrupt(enum gpio_signal signal) +{ + /* + * TODO(b/179513527): add USB-C support + */ +} diff --git a/board/gimble/usbc_config.h b/board/gimble/usbc_config.h new file mode 100644 index 0000000000..5d08a446fb --- /dev/null +++ b/board/gimble/usbc_config.h @@ -0,0 +1,22 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Brya board-specific USB-C configuration */ + +#ifndef __CROS_EC_USBC_CONFIG_H +#define __CROS_EC_USBC_CONFIG_H + +#define CONFIG_USB_PD_PORT_MAX_COUNT 3 + +enum usbc_port { + USBC_PORT_C0 = 0, + USBC_PORT_C1, + USBC_PORT_C2, + USBC_PORT_COUNT +}; + +void config_usb_db_type(void); + +#endif /* __CROS_EC_USBC_CONFIG_H */ diff --git a/board/gimble/vif_override.xml b/board/gimble/vif_override.xml new file mode 100644 index 0000000000..32736caf64 --- /dev/null +++ b/board/gimble/vif_override.xml @@ -0,0 +1,3 @@ +<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File + Definition from the USB-IF. +--> |