diff options
| author | Vijay Hiremath <vijay.p.hiremath@intel.com> | 2018-03-22 04:55:51 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-03-24 07:32:29 -0700 |
| commit | 3bd4e0de5edc6f62eda8739d31816b5b29d1979b (patch) | |
| tree | d6cc7049652e5fc41b765e0708e8722e4ca7bd24 /board | |
| parent | f59290878e5fcd99add71aec74baea7d1e3f0297 (diff) | |
| download | chrome-ec-3bd4e0de5edc6f62eda8739d31816b5b29d1979b.tar.gz | |
Code cleanup: Rename GPIO PCH_RCIN_L to SYS_RESET_L
Renamed GPIO PCH_RCIN_L to SYS_RESET_L so that all the Intel
chipset variants have same GPIO name for doing SOC internal reset.
BUG=b:72426192
BRANCH=none
TEST=make buildall -j
Change-Id: I931ce136743fa928dd7cf6f005c912db3b2da893
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/974241
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Diffstat (limited to 'board')
| -rw-r--r-- | board/bip/gpio.inc | 2 | ||||
| -rw-r--r-- | board/coral/gpio.inc | 2 | ||||
| -rw-r--r-- | board/glkrvp/gpio.inc | 2 | ||||
| -rw-r--r-- | board/it83xx_evb/gpio.inc | 2 | ||||
| -rw-r--r-- | board/reef/gpio.inc | 2 | ||||
| -rw-r--r-- | board/reef_it8320/gpio.inc | 2 | ||||
| -rw-r--r-- | board/yorp/gpio.inc | 4 |
7 files changed, 8 insertions, 8 deletions
diff --git a/board/bip/gpio.inc b/board/bip/gpio.inc index 5c65ed6382..b3b6e022f7 100644 --- a/board/bip/gpio.inc +++ b/board/bip/gpio.inc @@ -18,7 +18,7 @@ GPIO_INT(POWER_BUTTON_L, PIN(E, 4), GPIO_INT_BOTH, power_button_interrupt) /* ME * TODO(b/76023457): Move below 4 signals to virtual wires over eSPI */ GPIO(PCH_PLTRST_L, PIN(E, 3), GPIO_INPUT) /* PLT_RST_L: Platform Reset from SoC */ -GPIO(PCH_RCIN_L, PIN(B, 6), GPIO_ODR_HIGH) /* SYS_RST_ODL */ +GPIO(SYS_RESET_L, PIN(B, 6), GPIO_ODR_HIGH) /* SYS_RST_ODL */ GPIO(PCH_SMI_L, PIN(D, 4), GPIO_OUT_LOW) /* EC_SMI_R_ODL */ GPIO(PCH_SCI_L, PIN(D, 3), GPIO_OUT_LOW) /* EC_SCI_R_ODL */ diff --git a/board/coral/gpio.inc b/board/coral/gpio.inc index b9d4e15db0..a4f236a22c 100644 --- a/board/coral/gpio.inc +++ b/board/coral/gpio.inc @@ -111,7 +111,7 @@ GPIO(USB2_OTG_VBUSSENSE, PIN(9, 5), GPIO_OUTPUT) * be used. Set as input for now, we'll set it as an output when we want to use * it. Has external pull-down resistor. */ GPIO(EC_PCH_RTCRST, PIN(B, 7), GPIO_INPUT) -GPIO(PCH_RCIN_L, PIN(6, 1), GPIO_ODR_HIGH) /* SYS_RST_ODL */ +GPIO(SYS_RESET_L, PIN(6, 1), GPIO_ODR_HIGH) /* SYS_RST_ODL */ /* FIXME: What, if anything, to do about EC_RST_ODL on VCC1_RST#? */ diff --git a/board/glkrvp/gpio.inc b/board/glkrvp/gpio.inc index 2fc108b174..f66f903e97 100644 --- a/board/glkrvp/gpio.inc +++ b/board/glkrvp/gpio.inc @@ -34,7 +34,7 @@ GPIO_INT(AC_PRESENT, PIN(D, 2), GPIO_INT_BOTH, extpower_interrupt) GPIO_INT(WP_L, PIN(9, 3), GPIO_INT_BOTH | GPIO_SEL_1P8V, switch_interrupt) /* Power sequencing GPIOs */ -GPIO(PCH_RCIN_L, PIN(0, 0), GPIO_ODR_HIGH) +GPIO(SYS_RESET_L, PIN(0, 0), GPIO_ODR_HIGH) GPIO(PCH_RSMRST_L, PIN(0, 1), GPIO_OUT_LOW) GPIO(SMC_SHUTDOWN, PIN(3, 3), GPIO_OUT_LOW | GPIO_PULL_DOWN) GPIO(PCH_SYS_PWROK, PIN(3, 5), GPIO_OUT_LOW) diff --git a/board/it83xx_evb/gpio.inc b/board/it83xx_evb/gpio.inc index 96d362e4bd..c8a9c099ab 100644 --- a/board/it83xx_evb/gpio.inc +++ b/board/it83xx_evb/gpio.inc @@ -35,7 +35,7 @@ GPIO(USBPD_PORTA_VBUS_DROP, PIN(E, 5), GPIO_OUT_LOW) GPIO(PCH_SMI_L, PIN(D, 3), GPIO_OUT_HIGH) GPIO(PCH_SCI_L, PIN(D, 4), GPIO_OUT_HIGH) GPIO(GATE_A20_H, PIN(B, 5), GPIO_OUT_HIGH) -GPIO(PCH_RCIN_L, PIN(B, 6), GPIO_OUT_HIGH) +GPIO(SYS_RESET_L, PIN(B, 6), GPIO_OUT_HIGH) GPIO(LPC_CLKRUN_L, PIN(H, 0), GPIO_OUT_LOW) GPIO(PCH_WAKE_L, PIN(B, 7), GPIO_ODR_HIGH) /* Wake signal from EC to PCH */ diff --git a/board/reef/gpio.inc b/board/reef/gpio.inc index 8ea62c0590..95a45b17f7 100644 --- a/board/reef/gpio.inc +++ b/board/reef/gpio.inc @@ -121,7 +121,7 @@ GPIO(USB2_OTG_VBUSSENSE, PIN(9, 5), GPIO_OUTPUT) * be used. Set as input for now, we'll set it as an output when we want to use * it. Has external pull-down resistor. */ GPIO(EC_PCH_RTCRST, PIN(B, 7), GPIO_INPUT) -GPIO(PCH_RCIN_L, PIN(6, 1), GPIO_ODR_HIGH) /* SYS_RST_ODL */ +GPIO(SYS_RESET_L, PIN(6, 1), GPIO_ODR_HIGH) /* SYS_RST_ODL */ /* FIXME: What, if anything, to do about EC_RST_ODL on VCC1_RST#? */ diff --git a/board/reef_it8320/gpio.inc b/board/reef_it8320/gpio.inc index eee4835880..3d26bde426 100644 --- a/board/reef_it8320/gpio.inc +++ b/board/reef_it8320/gpio.inc @@ -40,7 +40,7 @@ GPIO(WIRELESS_GPIO_WLAN_POWER, PIN(B, 2), GPIO_ODR_HIGH) /* EN_PP3300_WLAN_ODL GPIO(EC_I2C_A_SCL, PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V) /* EC_I2C_GYRO_SCL */ GPIO(EC_I2C_A_SDA, PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V) /* EC_I2C_GYRO_SDA */ GPIO(ENABLE_BACKLIGHT, PIN(B, 5), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_BL_EN_OD */ -GPIO(PCH_RCIN_L, PIN(B, 6), GPIO_ODR_HIGH) /* SYS_RST_ODL */ +GPIO(SYS_RESET_L, PIN(B, 6), GPIO_ODR_HIGH) /* SYS_RST_ODL */ #ifndef CONFIG_POWER_S0IX GPIO(PCH_SLP_S0_L, PIN(B, 7), GPIO_INPUT) /* SLP_S0_L */ #endif diff --git a/board/yorp/gpio.inc b/board/yorp/gpio.inc index 1850d59b17..9b513f1fc8 100644 --- a/board/yorp/gpio.inc +++ b/board/yorp/gpio.inc @@ -41,10 +41,10 @@ GPIO(PCH_SLP_S0_L, PIN(A, 4), GPIO_INPUT) /* SLP_S0_L */ #endif /* - * TODO(b/74123961): Move PLT_RST_L and PCH_RCIN_L to virtual wires over eSPI + * TODO(b/74123961): Move PLT_RST_L and SYS_RESET_L to virtual wires over eSPI */ GPIO(PLT_RST_L, PIN(C, 7), GPIO_INPUT) /* Platform Reset from SoC */ -GPIO(PCH_RCIN_L, PIN(0, 2), GPIO_ODR_HIGH) /* SYS_RST_ODL */ +GPIO(SYS_RESET_L, PIN(0, 2), GPIO_ODR_HIGH) /* SYS_RST_ODL */ GPIO(ENTERING_RW, PIN(8, 0), GPIO_OUT_LOW) /* EC_ENTERING_RW */ GPIO(PCH_WAKE_L, PIN(7, 4), GPIO_ODR_HIGH) /* EC_PCH_WAKE_ODL */ |