diff options
| author | Randall Spangler <rspangler@chromium.org> | 2013-10-10 13:49:39 -0700 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2013-10-11 03:58:09 +0000 |
| commit | 1006187c61bee2a9700781e7a6fcd23b3cfad89b (patch) | |
| tree | 4a7f307cc1cf073933e982c8039ca87d83e7ab47 /board | |
| parent | a1191b92d2f5784e2f4e1c5f40d4af1a41e55fda (diff) | |
| download | chrome-ec-1006187c61bee2a9700781e7a6fcd23b3cfad89b.tar.gz | |
Add baytrail power sequencing
This is an initial version of power sequencing for the rambi rev.1
boards. It has a workaround for a rev.1 board problem; this requires
turning on PP5000 early.
BUG=chrome-os-partner:22895
BRANCH=none
TEST=AP should power on to S0 (PLTRST# deasserts) automatically when EC boots
Then 'apshutdown' should drag it back to G3.
Then 'powerbtn' should take it back to S0.
Change-Id: Id9bc6fe9b55fce3eb46ce1265891724ec7a4ae20
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172675
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'board')
| -rw-r--r-- | board/rambi/board.c | 2 | ||||
| -rw-r--r-- | board/rambi/board.h | 8 | ||||
| -rw-r--r-- | board/rambi/ec.tasklist | 2 |
3 files changed, 6 insertions, 6 deletions
diff --git a/board/rambi/board.c b/board/rambi/board.c index 38f4262fe4..72be16f3c0 100644 --- a/board/rambi/board.c +++ b/board/rambi/board.c @@ -77,7 +77,7 @@ const struct gpio_info gpio_list[] = { {"LPC_CLKRUN_L", LM4_GPIO_M, (1<<2), GPIO_ODR_HIGH, NULL}, {"PCH_CORE_PWROK", LM4_GPIO_F, (1<<5), GPIO_OUT_LOW, NULL}, {"PCH_PWRBTN_L", LM4_GPIO_H, (1<<0), GPIO_ODR_HIGH, NULL}, - {"PCH_RCIN_L", LM4_GPIO_F, (1<<3), GPIO_ODR_LOW, NULL}, + {"PCH_RCIN_L", LM4_GPIO_F, (1<<3), GPIO_ODR_HIGH, NULL}, {"PCH_RSMRST_L", LM4_GPIO_F, (1<<1), GPIO_OUT_LOW, NULL}, {"PCH_SMI_L", LM4_GPIO_F, (1<<4), GPIO_ODR_HIGH, NULL}, {"PCH_SOC_OVERRIDE_L", LM4_GPIO_G, (1<<1), GPIO_OUT_HIGH, NULL}, diff --git a/board/rambi/board.h b/board/rambi/board.h index deb00abc15..2cc95f1fb1 100644 --- a/board/rambi/board.h +++ b/board/rambi/board.h @@ -11,6 +11,9 @@ /* Optional features */ #define CONFIG_BACKLIGHT_LID #define CONFIG_BOARD_VERSION +#define CONFIG_CHIPSET_BAYTRAIL +#define CONFIG_CHIPSET_CAN_THROTTLE +#define CONFIG_CHIPSET_X86 #define CONFIG_CMD_GSV #define CONFIG_EXTPOWER_GPIO #define CONFIG_KEYBOARD_COL2_INVERTED @@ -35,9 +38,6 @@ #define CONFIG_CHARGER_INPUT_CURRENT 4032 /* mA, about half max */ #define CONFIG_CHARGER_SENSE_RESISTOR 10 /* Charge sense resistor, mOhm */ #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* Input sensor resistor, mOhm */ -#define CONFIG_CHIPSET_CAN_THROTTLE -#define CONFIG_CHIPSET_HASWELL -#define CONFIG_CHIPSET_X86 #define CONFIG_USB_PORT_POWER_DUMB #endif @@ -107,7 +107,7 @@ enum gpio_signal { GPIO_LPC_CLKRUN_L, /* Request that PCH drive LPC clock */ GPIO_PCH_CORE_PWROK, /* Indicate core well power is stable */ GPIO_PCH_PWRBTN_L, /* Power button output to PCH */ - GPIO_PCH_RCIN_L, /* RCIN# line to PCH (for 8042 emulation) */ + GPIO_PCH_RCIN_L, /* Reset line to PCH (for 8042 emulation) */ GPIO_PCH_RSMRST_L, /* Reset PCH resume power plane logic */ GPIO_PCH_SMI_L, /* System management interrupt to PCH */ GPIO_PCH_SOC_OVERRIDE_L, /* SOC override signal to PCH; when high, ME diff --git a/board/rambi/ec.tasklist b/board/rambi/ec.tasklist index a3c01c171b..fd3c29ac1b 100644 --- a/board/rambi/ec.tasklist +++ b/board/rambi/ec.tasklist @@ -22,7 +22,7 @@ TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \ TASK_NOTEST(VBOOTHASH, vboot_hash_task, NULL, LARGER_TASK_STACK_SIZE) \ /* TASK_ALWAYS(CHARGER, charger_task, NULL, TASK_STACK_SIZE) */ \ - /* TASK_NOTEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE) */ \ + TASK_NOTEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE) \ TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \ TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \ TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \ |