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| author | Allen-kh Cheng <allen-kh.cheng@mediatek.corp-partner.google.com> | 2022-08-24 13:20:12 +0800 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-08-26 10:59:29 +0000 |
| commit | 5d5611dfa23fda1f3f692316f0039b471dc903c0 (patch) | |
| tree | 91317d46644e127dd171d68af9d19ae25d0e35ce /board | |
| parent | 573bcf3ac69bc9e8a4bb79f3cf0bd4a6ea49026d (diff) | |
| download | chrome-ec-5d5611dfa23fda1f3f692316f0039b471dc903c0.tar.gz | |
mtk_scp: Enable I/D-cache for mt8186
1. Enable cache mapping on scp boot.
2. Add interrupt disable/enable to prevent preempt when setting cache
range.
BRANCH=none
BUG=b:218771968
TEST=Boot kukui scp and open cam ok
make BOARD=corsola_scp -j ALLOW_CONFIG=1
Signed-off-by: Allen-kh Cheng <allen-kh.cheng@mediatek.corp-partner.google.com>
Change-Id: I8d586afc33cba55d388d553dd2a2fc2047089553
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3853765
Commit-Queue: Hsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: Wei-Shun Chang <weishunc@chromium.org>
Diffstat (limited to 'board')
| -rw-r--r-- | board/kukui_scp/board.h | 39 |
1 files changed, 33 insertions, 6 deletions
diff --git a/board/kukui_scp/board.h b/board/kukui_scp/board.h index bc4b5a0dda..16aba19948 100644 --- a/board/kukui_scp/board.h +++ b/board/kukui_scp/board.h @@ -27,10 +27,12 @@ #define CONFIG_HOSTCMD_ALIGNED /* + * mt8183: + * * RW only, no flash * +-------------------- 0x0 * | ROM vectortable, .text, .rodata, .data LMA - * +-------------------- 0x10000 + * +-------------------- 0x58000 * | RAM .bss, .data * +-------------------- 0x7BDB0 * | IPI shared buffer with AP (288 + 8) * 2 @@ -40,11 +42,23 @@ * | 8KB D-CACHE * +-------------------- 0x80000 */ -#ifdef CHIP_VARIANT_MT8186 -#define ICACHE_BASE 0x3E000 -#else -#define ICACHE_BASE 0x7C000 -#endif + +/* + * mt8186: + * + * RW only, no flash + * +-------------------- 0x0 + * | ROM vectortable, .text, .rodata, .data LMA + * +-------------------- 0x2C000 + * | RAM .bss, .data + * +-------------------- 0x3BDB0 + * | IPI shared buffer with AP (288 + 8) * 2 => 0x250 + * +-------------------- 0x3C000 + * | 8KB I-CACHE + * +-------------------- 0x3E000 + * | 8KB D-CACHE + * +-------------------- 0x40000 + */ #define CONFIG_ROM_BASE 0x0 @@ -54,6 +68,12 @@ #define CONFIG_RAM_BASE 0x58000 #endif +#ifdef CHIP_VARIANT_MT8186 +#define ICACHE_BASE 0x3C000 +#else +#define ICACHE_BASE 0x7C000 +#endif + #define CONFIG_ROM_SIZE (CONFIG_RAM_BASE - CONFIG_ROM_BASE) #define CONFIG_RAM_SIZE (CONFIG_IPC_SHARED_OBJ_ADDR - CONFIG_RAM_BASE) #define CONFIG_CODE_RAM_SIZE CONFIG_RAM_BASE @@ -64,7 +84,14 @@ #define CONFIG_DRAM_BASE 0x10000000 /* Shared memory address in AP physical address space. */ #define CONFIG_DRAM_BASE_LOAD 0x50000000 + +#ifdef CHIP_VARIANT_MT8186 +#define CONFIG_DRAM_SIZE 0x010a0000 /* 16 MB */ +#define CACHE_TRANS_AP_SIZE 0x010a0000 +#else #define CONFIG_DRAM_SIZE 0x01400000 /* 20 MB */ +#define CACHE_TRANS_AP_SIZE 0x00400000 +#endif /* IPI configs */ #define CONFIG_IPC_SHARED_OBJ_BUF_SIZE 288 |