diff options
| author | Kyoung Kim <kyoung.il.kim@intel.com> | 2015-05-22 18:40:41 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-07-15 02:06:09 +0000 |
| commit | 562c10e4b51431bbae7b32bb37769a0a595db875 (patch) | |
| tree | 90cc7c28913543476e566091ab8b26708f4ee6e4 /board | |
| parent | 88ef0bc44e1b3296a75e17011ae2ffb11883f8f7 (diff) | |
| download | chrome-ec-562c10e4b51431bbae7b32bb37769a0a595db875.tar.gz | |
Cyan: Enable PG3 for Cyan
Enable SOC G3 and Psuedo G3 for Cyan
BUG=none
TEST=Cyan EVT
BRANCH=none
Change-Id: Iaaa535786b1ac7485414f3bfb902357501fe47f5
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/283553
Reviewed-by: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
Tested-by: Divya Jyothi <divya.jyothi@intel.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/cyan/board.h | 1 | ||||
| -rw-r--r-- | board/cyan/gpio.inc | 25 |
2 files changed, 17 insertions, 9 deletions
diff --git a/board/cyan/board.h b/board/cyan/board.h index dd4daa0818..6d37516ba0 100644 --- a/board/cyan/board.h +++ b/board/cyan/board.h @@ -23,6 +23,7 @@ #define CONFIG_POWER_BUTTON #define CONFIG_POWER_BUTTON_X86 #define CONFIG_LID_SWITCH +#define CONFIG_LOW_POWER_PSEUDO_G3 #define CONFIG_LED_COMMON #define CONFIG_POWER_COMMON #define CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5 diff --git a/board/cyan/gpio.inc b/board/cyan/gpio.inc index 44dd70920a..cf4eaf5ce0 100644 --- a/board/cyan/gpio.inc +++ b/board/cyan/gpio.inc @@ -5,14 +5,14 @@ * found in the LICENSE file. */ -GPIO_INT(LID_OPEN, PIN(27), GPIO_INT_BOTH, lid_interrupt) /* Lid switch */ -GPIO_INT(AC_PRESENT, PIN(30), GPIO_INT_BOTH, extpower_interrupt) /* BC_ACOK / EC_ACIN - to know if battery or AC connected */ -GPIO_INT(WP_L, PIN(33), GPIO_INT_BOTH, switch_interrupt) /* Write protect input */ -GPIO_INT(POWER_BUTTON_L, PIN(35), GPIO_INT_BOTH, power_button_interrupt) /* Power button */ -GPIO_INT(RSMRST_L_PGOOD, PIN(63), GPIO_INT_BOTH, power_signal_interrupt) /* RSMRST_N_PWRGD from power logic */ -GPIO_INT(ALL_SYS_PGOOD, PIN(130), GPIO_INT_BOTH, power_signal_interrupt) /* ALL_SYS_PWRGD from power logic */ -GPIO_INT(PCH_SLP_S4_L, PIN(200), GPIO_INT_BOTH | GPIO_PULL_UP, power_signal_interrupt) /* SLP_S4# signal from PCH */ -GPIO_INT(PCH_SLP_S3_L, PIN(206), GPIO_INT_BOTH | GPIO_PULL_UP, power_signal_interrupt) /* SLP_S3# signal from PCH */ +GPIO_INT(LID_OPEN, PIN(27), GPIO_INT_BOTH_DSLEEP, lid_interrupt) /* Lid switch */ +GPIO_INT(AC_PRESENT, PIN(30), GPIO_INT_BOTH_DSLEEP, extpower_interrupt) /* BC_ACOK / EC_ACIN - to know if battery or AC connected */ +GPIO_INT(WP_L, PIN(33), GPIO_INT_BOTH, switch_interrupt) /* Write protect input */ +GPIO_INT(POWER_BUTTON_L, PIN(35), GPIO_INT_BOTH_DSLEEP, power_button_interrupt) /* Power button */ +GPIO_INT(RSMRST_L_PGOOD, PIN(63), GPIO_INT_BOTH, power_signal_interrupt) /* RSMRST_N_PWRGD from power logic */ +GPIO_INT(ALL_SYS_PGOOD, PIN(130), GPIO_INT_BOTH_DSLEEP, power_signal_interrupt) /* ALL_SYS_PWRGD from power logic */ +GPIO_INT(PCH_SLP_S4_L, PIN(200), GPIO_INT_BOTH_DSLEEP, power_signal_interrupt) /* SLP_S4# signal from PCH */ +GPIO_INT(PCH_SLP_S3_L, PIN(206), GPIO_INT_BOTH_DSLEEP, power_signal_interrupt) /* SLP_S3# signal from PCH */ GPIO(NC_012, PIN(12), GPIO_INPUT | GPIO_PULL_UP) /* NC */ GPIO(USB_ILIM_SEL, PIN(13), GPIO_OUT_HIGH) /* USB current control */ @@ -49,7 +49,7 @@ GPIO(NC_57, PIN(57), GPIO_INPUT | GPIO_PULL_UP) /* NC */ GPIO(CHGR_PMON, PIN(60), GPIO_ANALOG) GPIO(WIFI_PWREN, PIN(61), GPIO_OUT_HIGH) /* Enable power for WiFi */ GPIO(BATT_EN_L, PIN(62), GPIO_INPUT) /* Will be NC */ -GPIO(NC_64, PIN(64), GPIO_INPUT | GPIO_PULL_UP) /* NC */ +GPIO(EC_HIB_L, PIN(64), GPIO_OUT_LOW) GPIO(PCH_SYS_PWROK, PIN(65), GPIO_OUT_LOW) /* EC thinks everything is up and ready (DELAY_ALL_SYS_PWRGD) */ GPIO(PCH_WAKE_L, PIN(66), GPIO_ODR_HIGH) /* PCH wake pin */ GPIO(USB1_ENABLE, PIN(67), GPIO_OUT_LOW) /* Enable power for USB3 Port */ @@ -111,6 +111,7 @@ ALTERNATE(PIN_MASK(10, 0xd8), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT) #else ALTERNATE(PIN_MASK(0, 0x02), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT_COL2) #endif + ALTERNATE(PIN_MASK(3, 0x04), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) ALTERNATE(PIN_MASK(4, 0x0d), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) ALTERNATE(PIN_MASK(12, 0x60), 2, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) @@ -124,3 +125,9 @@ ALTERNATE(PIN_MASK(12, 0x01), 1, MODULE_LPC, 0) ALTERNATE(PIN_MASK(5, 0x10), 1, MODULE_SPI, 0) /* 54: MOSI */ ALTERNATE(PIN_MASK(16, 0x10), 1, MODULE_SPI, 0) /* 164: MISO */ ALTERNATE(PIN_MASK(15, 0x08), 1, MODULE_SPI, 0) /* 153: CLK */ + +/* Re-Config LPC Pins to GPIO Open Drain for SOC G3 (EC - POWER_G3) state */ +ALTERNATE(PIN_MASK(1, 0x10), 0, MODULE_GPIO, GPIO_ODR_HIGH) /* 14: LPC CLKRUN */ +ALTERNATE(PIN_MASK(11, 0x9e), 0, MODULE_GPIO, GPIO_ODR_HIGH) /* 111~114:LAD[0:3], 117:PCI_CLK */ +ALTERNATE(PIN_MASK(11, 0x40), 0, MODULE_GPIO, GPIO_ODR_HIGH) /* 116: LRESET# */ +ALTERNATE(PIN_MASK(12, 0x01), 0, MODULE_GPIO, GPIO_ODR_HIGH) /* 120: LFRAME# */ |