ss-mux: update semantics for TCPC/MUX only used as MUX

This converts the compile time option of
CONFIG_USB_PD_TCPM_TCPCI_MUX_ONLY into a runtime option to better
support draggon egg designs and reduce CONFIG complexity in general.

Introduce new mux_read/write to read from tcpc_config_t or mux driver
depending on new flag setting.

Audited all mux drivers for any use of tcpc_read/write and updated to
mux_read/write.

BRANCH=none
BUG=b:110937880
TEST=On Bip with CL stack:
     Verified by connecting DP monitor at boot;
     Verified plug / unplug of DP cable works;

Change-Id: I968893b886ff0ccc4074beae5ec42973814ae77c
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1200062
Commit-Ready: Gaggery Tsai <gaggery.tsai@intel.corp-partner.google.com>
Reviewed-by: Scott Collyer <scollyer@chromium.org>

5 files changed, 10 insertions, 12 deletions

diff --git a/board/chell/board.c b/board/chell/board.c
index 5fc0a47965..a3f7875166 100644
--- a/board/chell/board.c
+++ b/board/chell/board.c
@@ -171,10 +171,10 @@ struct pi3usb9281_config pi3usb9281_chips[] = {
 BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) ==
 	     CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT);
 
-static int ps874x_tune_mux(const struct usb_mux *mux)
+static int ps874x_tune_mux(int port)
 {
 	/* Apply same USB EQ settings to both Type-C mux */
-	ps874x_tune_usb_eq(mux->port_addr,
+	ps874x_tune_usb_eq(port,
 			   PS874X_USB_EQ_TX_6_5_DB,
 			   PS874X_USB_EQ_RX_14_3_DB);
 
diff --git a/board/coral/board.c b/board/coral/board.c
index bc37b92d13..2cf54638e5 100644
--- a/board/coral/board.c
+++ b/board/coral/board.c
@@ -278,10 +278,10 @@ const enum gpio_signal hibernate_wake_pins[] = {
 
 const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
-static int ps8751_tune_mux(const struct usb_mux *mux)
+static int ps8751_tune_mux(int port)
 {
 	/* 0x98 sets lower EQ of DP port (4.5db) */
-	tcpc_write(mux->port_addr, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98);
+	mux_write(port, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98);
 	return EC_SUCCESS;
 }
 
diff --git a/board/fizz/board.c b/board/fizz/board.c
index fdc4a5620e..2c2877c0c1 100644
--- a/board/fizz/board.c
+++ b/board/fizz/board.c
@@ -201,11 +201,10 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_COUNT] = {
 			TCPC_ALERT_ACTIVE_LOW},
 };
 
-static int ps8751_tune_mux(const struct usb_mux *mux)
+static int ps8751_tune_mux(int port)
 {
 	/* 0x98 sets lower EQ of DP port (4.5db) */
-	i2c_write8(I2C_PORT_TCPC0, I2C_ADDR_TCPC0,
-			   PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98);
+	mux_write(port, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98);
 	return EC_SUCCESS;
 }
 
diff --git a/board/reef/board.c b/board/reef/board.c
index 6df8b781ef..d5cbe46099 100644
--- a/board/reef/board.c
+++ b/board/reef/board.c
@@ -283,10 +283,10 @@ const enum gpio_signal hibernate_wake_pins[] = {
 
 const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
-static int ps8751_tune_mux(const struct usb_mux *mux)
+static int ps8751_tune_mux(int port)
 {
 	/* 0x98 sets lower EQ of DP port (4.5db) */
-	tcpc_write(mux->port_addr, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98);
+	mux_write(port, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98);
 	return EC_SUCCESS;
 }
 
diff --git a/board/reef_mchp/board.c b/board/reef_mchp/board.c
index 4efe7dcdb3..81d6134915 100644
--- a/board/reef_mchp/board.c
+++ b/board/reef_mchp/board.c
@@ -413,13 +413,12 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
  * results taking up to 10ms before I2C communication with PS8751
  * is stable. Don't know how to fix this.
  */
-static int ps8751_tune_mux(const struct usb_mux *mux)
+static int ps8751_tune_mux(int port)
 {
 	int rv;
 
 	/* 0x98 sets lower EQ of DP port (4.5db) */
-	rv = i2c_write8(MCHP_I2C_PORT2, 0x16,
-		PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98);
+	rv = mux_write(port, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98);
 
 	/* TCPCI spec. delay msleep(6); */