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| author | Shaunak Saha <shaunak.saha@intel.com> | 2015-12-15 23:09:08 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-01-20 23:21:55 -0800 |
| commit | d83482a3b0d242ef4b6fa76500fc58a5c5c48122 (patch) | |
| tree | 47113e4224febcf0f8672380bf288217a4de8ace /board | |
| parent | c992cb217ebf22ada7ac7d76c56b0a44ace2c799 (diff) | |
| download | chrome-ec-d83482a3b0d242ef4b6fa76500fc58a5c5c48122.tar.gz | |
Kunimitsu: Set the power button debounce time to zero in PMIC
To reduce the boot & resume time in EC, set the power button
debounce time to zero in PMIC PBCONFIG Register.
BRANCH=glados
BUG=None
TEST=Put the device in S3. Press the power button and observe
SLP_SUS_S3 is getting released 30ms earlier than the previous
configuration
Change-Id: I184fa056b9b6aed1bcccae9f38eaff3f3bb4e2bb
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/321341
Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'board')
| -rw-r--r-- | board/kunimitsu/board.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/board/kunimitsu/board.c b/board/kunimitsu/board.c index 15f825cd44..2a899c3392 100644 --- a/board/kunimitsu/board.c +++ b/board/kunimitsu/board.c @@ -486,6 +486,16 @@ static void board_pmic_init(void) if (ret) goto pmic_error; + /* + * PBCONFIG Register configuration + * [7] : 1b Power button debounce, 0ms (no debounce) + * [6] : 0b Power button reset timer logic, no action (default) + * [5:0] : 011111b Force an Emergency reset time, 31s (default) + */ + ret = I2C_PMIC_WRITE(TPS650830_REG_PBCONFIG, 0x9F); + if (ret) + goto pmic_error; + CPRINTS("PMIC initialization done"); return; |