board: Add initial nocturne support.

BUG=b:78539498
BRANCH=None
TEST=make -j BOARD=nocturne

Change-Id: I830ff6739fb648625536ba248eeb383797c850e2
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1032094
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>

9 files changed, 1752 insertions, 0 deletions

diff --git a/board/nocturne/base_detect.c b/board/nocturne/base_detect.c
new file mode 100644
index 0000000000..a75aba5cbd
--- /dev/null
+++ b/board/nocturne/base_detect.c
@@ -0,0 +1,249 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Nocturne base detection code.
+ *
+ * Nocturne has two analog detection pins with which it monitors to determine
+ * the base status: the attach, and detach pins.
+ *
+ * When the voltages cross a certain threshold, after some debouncing, the base
+ * is deemed connected.  Nocturne then applies the base power and monitors for
+ * power faults from the eFuse as well as base disconnection.  Similarly, once
+ * the voltages cross a different threshold, after some debouncing, the base is
+ * deemed disconnected.  At this point, Nocturne disables the base power.
+ */
+
+#include "adc.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "tablet_mode.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
+
+#define DEFAULT_POLL_TIMEOUT_US (250 * MSEC)
+#define DEBOUNCE_TIMEOUT_US (20 * MSEC)
+#define POWER_FAULT_RETRY_INTERVAL_US (15 * MSEC)
+
+/*
+ * Number of times to attempt re-applying power within 1s when a fault occurs.
+ */
+#define POWER_FAULT_MAX_RETRIES 3
+
+/* Thresholds for attach pin reading when power is not applied. */
+#define ATTACH_MIN_MV 300
+#define ATTACH_MAX_MV 800
+
+/* Threshold for attach pin reading when power IS applied. */
+#define PWREN_ATTACH_MIN_MV 2300
+
+/* Threshold for detach pin reading. */
+#define DETACH_MIN_MV 10
+
+
+enum base_detect_state {
+	BASE_DETACHED = 0,
+	BASE_ATTACHED_DEBOUNCE,
+	BASE_ATTACHED,
+	BASE_DETACHED_DEBOUNCE,
+};
+
+static int debug;
+static enum base_detect_state state;
+
+static void base_detect_changed(void)
+{
+	switch (state) {
+	case BASE_DETACHED:
+		/* Indicate that we are in tablet mode. */
+		tablet_set_mode(1);
+
+		/*
+		 * Disable power fault interrupt.  It will read low when base
+		 * power is removed.
+		 */
+		gpio_disable_interrupt(GPIO_BASE_PWR_FAULT_ODL);
+		/* Now, remove power to the base. */
+		gpio_set_level(GPIO_BASE_PWR_EN, 0);
+		break;
+
+	case BASE_ATTACHED:
+		/*
+		 * TODO(b/73133611): Note, this simple logic may suffice for
+		 * now, but we may have to revisit this.
+		 */
+		tablet_set_mode(0);
+
+		/* Apply power to the base. */
+		gpio_set_level(GPIO_BASE_PWR_EN, 1);
+		/* Allow time for the fault line to rise. */
+		msleep(1);
+		/* Monitor for base power faults. */
+		gpio_enable_interrupt(GPIO_BASE_PWR_FAULT_ODL);
+		break;
+
+	default:
+		return;
+	};
+}
+
+static int base_seems_attached(int attach_pin_mv, int detach_pin_mv)
+{
+	/* We can't tell if we don't have good readings. */
+	if (attach_pin_mv == ADC_READ_ERROR ||
+	    detach_pin_mv == ADC_READ_ERROR)
+		return 0;
+
+	if (gpio_get_level(GPIO_BASE_PWR_EN))
+		return (attach_pin_mv >= PWREN_ATTACH_MIN_MV) &&
+			(detach_pin_mv >= DETACH_MIN_MV);
+	else
+		return (attach_pin_mv <= ATTACH_MAX_MV) &&
+			(attach_pin_mv >= ATTACH_MIN_MV) &&
+			(detach_pin_mv <= DETACH_MIN_MV);
+}
+
+static int base_seems_detached(int attach_pin_mv, int detach_pin_mv)
+{
+	/* We can't tell if we don't have good readings. */
+	if (attach_pin_mv == ADC_READ_ERROR ||
+	    detach_pin_mv == ADC_READ_ERROR)
+		return 0;
+
+	return (attach_pin_mv >= PWREN_ATTACH_MIN_MV) &&
+		(detach_pin_mv <= DETACH_MIN_MV);
+}
+
+static void set_state(enum base_detect_state new_state)
+{
+	if (new_state != state) {
+		CPRINTS("BD: st%d", new_state);
+		state = new_state;
+	}
+}
+
+static void base_detect_deferred(void);
+DECLARE_DEFERRED(base_detect_deferred);
+static void base_detect_deferred(void)
+{
+	int attach_reading;
+	int detach_reading;
+	int timeout = DEFAULT_POLL_TIMEOUT_US;
+
+	attach_reading = adc_read_channel(ADC_BASE_ATTACH);
+	detach_reading = adc_read_channel(ADC_BASE_DETACH);
+
+	if (debug)
+		CPRINTS("BD st%d: att: %dmV det: %dmV", state,
+			attach_reading,
+			detach_reading);
+
+	switch (state) {
+	case BASE_DETACHED:
+		/* Check to see if a base may be attached. */
+		if (base_seems_attached(attach_reading, detach_reading)) {
+			timeout = DEBOUNCE_TIMEOUT_US;
+			set_state(BASE_ATTACHED_DEBOUNCE);
+		}
+		break;
+
+	case BASE_ATTACHED_DEBOUNCE:
+		/* Check to see if it's still attached. */
+		if (base_seems_attached(attach_reading, detach_reading)) {
+			set_state(BASE_ATTACHED);
+			base_detect_changed();
+		} else if (base_seems_detached(attach_reading,
+					       detach_reading)) {
+			set_state(BASE_DETACHED);
+		}
+		break;
+
+	case BASE_ATTACHED:
+		/* Check to see if a base may be detached. */
+		if (base_seems_detached(attach_reading, detach_reading)) {
+			timeout = DEBOUNCE_TIMEOUT_US;
+			set_state(BASE_DETACHED_DEBOUNCE);
+		}
+		break;
+
+	case BASE_DETACHED_DEBOUNCE:
+		/* Check to see if a base is still detached. */
+		if (base_seems_detached(attach_reading, detach_reading)) {
+			set_state(BASE_DETACHED);
+			base_detect_changed();
+		} else if (base_seems_attached(attach_reading,
+					       detach_reading)) {
+			set_state(BASE_ATTACHED);
+		}
+		break;
+		/* TODO(b/74239259): do you want to add an interrupt? */
+
+	default:
+		break;
+	};
+
+	/* Check again in the appropriate time. */
+	hook_call_deferred(&base_detect_deferred_data, timeout);
+};
+DECLARE_HOOK(HOOK_INIT, base_detect_deferred, HOOK_PRIO_INIT_ADC + 1);
+
+static uint8_t base_power_on_attempts;
+static void clear_base_power_on_attempts_deferred(void)
+{
+	base_power_on_attempts = 0;
+}
+DECLARE_DEFERRED(clear_base_power_on_attempts_deferred);
+
+static void check_and_reapply_base_power_deferred(void)
+{
+	if (state != BASE_ATTACHED)
+		return;
+
+	if (base_power_on_attempts < POWER_FAULT_MAX_RETRIES) {
+		CPRINTS("Reapply base pwr");
+		gpio_set_level(GPIO_BASE_PWR_EN, 1);
+		base_power_on_attempts++;
+
+		hook_call_deferred(&clear_base_power_on_attempts_deferred_data,
+				   SECOND);
+	}
+
+}
+DECLARE_DEFERRED(check_and_reapply_base_power_deferred);
+
+void base_pwr_fault_interrupt(enum gpio_signal s)
+{
+	/* Inverted because active low. */
+	int fault_detected = !gpio_get_level(GPIO_BASE_PWR_FAULT_ODL);
+
+	if (fault_detected) {
+		/* Turn off base power. */
+		CPRINTS("Base Pwr Flt!");
+		gpio_set_level(GPIO_BASE_PWR_EN, 0);
+
+		/*
+		 * Try and apply power in a bit if maybe it was just a temporary
+		 * condition.
+		 */
+		hook_call_deferred(&check_and_reapply_base_power_deferred_data,
+				   POWER_FAULT_RETRY_INTERVAL_US);
+	}
+}
+
+static int command_basedetectdebug(int argc, char **argv)
+{
+	if ((argc > 1) && !parse_bool(argv[1], &debug))
+		return EC_ERROR_PARAM1;
+
+	CPRINTS("BD: st%d", state);
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(basedebug, command_basedetectdebug, "[ena|dis]",
+			"En/Disable base detection debug");
diff --git a/board/nocturne/battery.c b/board/nocturne/battery.c
new file mode 100644
index 0000000000..3bfb6843aa
--- /dev/null
+++ b/board/nocturne/battery.c
@@ -0,0 +1,87 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery.h"
+#include "battery_smart.h"
+#include "common.h"
+#include "ec_commands.h"
+#include "extpower.h"
+
+/* Shutdown mode parameter to write to manufacturer access register */
+#define SB_SHUTDOWN_DATA	0x0010
+
+/* Battery info */
+static const struct battery_info info = {
+	.voltage_max		= 8880,
+	.voltage_normal		= 7700,
+	.voltage_min		= 6000,
+	.precharge_current	= 160,
+	.start_charging_min_c	= 10,
+	.start_charging_max_c	= 50,
+	.charging_min_c		= 10,
+	.charging_max_c		= 50,
+	.discharging_min_c	= -20,
+	.discharging_max_c	= 60,
+};
+
+int board_cut_off_battery(void)
+{
+	int rv;
+
+	/* Ship mode command must be sent twice to take effect */
+	rv = sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
+	if (rv != EC_SUCCESS)
+		return EC_RES_ERROR;
+
+	rv = sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
+	return rv ? EC_RES_ERROR : EC_RES_SUCCESS;
+}
+
+const struct battery_info *battery_get_info(void)
+{
+	return &info;
+}
+
+enum battery_disconnect_state battery_get_disconnect_state(void)
+{
+	uint8_t data[6];
+	int rv;
+
+	/*
+	 * Take note if we find that the battery isn't in disconnect state,
+	 * and always return NOT_DISCONNECTED without probing the battery.
+	 * This assumes the battery will not go to disconnect state during
+	 * runtime.
+	 */
+	static int not_disconnected;
+
+	if (not_disconnected)
+		return BATTERY_NOT_DISCONNECTED;
+
+	/* Check if battery charging + discharging is disabled. */
+	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS,
+			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
+	if (rv)
+		return BATTERY_DISCONNECT_ERROR;
+	if (~data[3] & (BATTERY_DISCHARGING_DISABLED |
+			BATTERY_CHARGING_DISABLED)) {
+		not_disconnected = 1;
+		return BATTERY_NOT_DISCONNECTED;
+	}
+
+	/*
+	 * Battery is neither charging nor discharging. Verify that
+	 * we didn't enter this state due to a safety fault.
+	 */
+	rv = sb_read_mfgacc(PARAM_SAFETY_STATUS,
+			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
+	if (rv || data[2] || data[3] || data[4] || data[5])
+		return BATTERY_DISCONNECT_ERROR;
+
+	/* No safety fault, battery is disconnected */
+	return BATTERY_DISCONNECTED;
+}
diff --git a/board/nocturne/board.c b/board/nocturne/board.c
new file mode 100644
index 0000000000..ee9d924c93
--- /dev/null
+++ b/board/nocturne/board.c
@@ -0,0 +1,510 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Nocturne board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charge_state_v2.h"
+#include "common.h"
+#include "console.h"
+#include "compile_time_macros.h"
+#include "driver/accelgyro_bmi160.h"
+#include "driver/als_opt3001.h"
+#include "driver/ppc/sn5s330.h"
+#include "driver/sync.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "lid_switch.h"
+#include "motion_sense.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "registers.h"
+#include "system.h"
+#include "switch.h"
+#include "task.h"
+#include "tcpci.h"
+#include "usb_mux.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+
+static void tcpc_alert_event(enum gpio_signal s)
+{
+#ifdef HAS_TASK_PDCMD
+	/* Exchange status with TCPCs */
+	host_command_pd_send_status(PD_CHARGE_NO_CHANGE);
+#endif
+}
+
+/*
+ * Nocturne shares the TCPC Alert# line with the TI SN5S330's interrupt line.
+ * Therefore, we need to also check on that part.
+ */
+static void usb_c_interrupt(enum gpio_signal s)
+{
+	int port = (s == GPIO_USB_C0_PD_INT_ODL) ? 0 : 1;
+
+	tcpc_alert_event(s);
+	sn5s330_interrupt(port);
+}
+
+#include "gpio_list.h"
+
+const enum gpio_signal hibernate_wake_pins[] = {
+	GPIO_LID_OPEN,
+	GPIO_AC_PRESENT,
+	GPIO_POWER_BUTTON_L,
+};
+const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
+
+const struct adc_t adc_channels[] = {
+	[ADC_BASE_ATTACH] = {
+		"BASE ATTACH", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
+	},
+
+	[ADC_BASE_DETACH] = {
+		"BASE DETACH", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
+	},
+};
+
+/* Power signal list.  Must match order of enum power_signal. */
+const struct power_signal_info power_signal_list[] = {
+	{GPIO_SLP_S0_L,
+	 POWER_SIGNAL_ACTIVE_HIGH | POWER_SIGNAL_DISABLE_AT_BOOT,
+	 "SLP_S0_DEASSERTED"},
+	{GPIO_SLP_S3_L,		POWER_SIGNAL_ACTIVE_HIGH, "SLP_S3_DEASSERTED"},
+	{GPIO_SLP_S4_L,		POWER_SIGNAL_ACTIVE_HIGH, "SLP_S4_DEASSERTED"},
+	{GPIO_PCH_SLP_SUS_L,	POWER_SIGNAL_ACTIVE_HIGH, "SLP_SUS_DEASSERTED"},
+	{GPIO_RSMRST_L_PGOOD,	POWER_SIGNAL_ACTIVE_HIGH, "RSMRST_L_PGOOD"},
+	{GPIO_PMIC_DPWROK,	POWER_SIGNAL_ACTIVE_HIGH, "PMIC_DPWROK"},
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_DB0_LED_RED] =   { 3, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				   2400 },
+	[PWM_CH_DB0_LED_GREEN] = { 0, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				   2400 },
+	[PWM_CH_DB0_LED_BLUE] =  { 2, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				   2400 },
+	[PWM_CH_DB1_LED_RED] =   { 7, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				   2400 },
+	[PWM_CH_DB1_LED_GREEN] = { 5, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				   2400 },
+	[PWM_CH_DB1_LED_BLUE] =  { 6, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				   2400 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* I2C port map */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		"battery", I2C_PORT_BATTERY, 100, GPIO_EC_I2C4_BATTERY_SCL,
+		GPIO_EC_I2C4_BATTERY_SDA
+	},
+
+	{
+		"power", I2C_PORT_POWER, 100, GPIO_EC_I2C0_POWER_SCL,
+		GPIO_EC_I2C0_POWER_SDA
+	},
+
+	/* TODO(aaboagye): Restore 1MHz bus speed for after eval. */
+	{
+		"als_gyro", I2C_PORT_ALS_GYRO, 100, GPIO_EC_I2C5_ALS_GYRO_SCL,
+		GPIO_EC_I2C5_ALS_GYRO_SDA
+	},
+
+	{
+		"usbc0", I2C_PORT_USB_C0, 100, GPIO_USB_C0_SCL, GPIO_USB_C0_SDA
+	},
+
+	{
+		"usbc1", I2C_PORT_USB_C1, 100, GPIO_USB_C1_SCL, GPIO_USB_C1_SDA
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+
+/*
+ * Motion Sense
+ */
+
+/* Lid Sensor mutex */
+static struct mutex g_lid_mutex;
+
+/* Sensor driver data */
+static struct bmi160_drv_data_t g_bmi160_data;
+static struct opt3001_drv_data_t g_opt3001_data = {
+	.scale = 1,
+	.uscale = 0,
+	.offset = 0,
+};
+
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "BMI160 ACC",
+		.active_mask = SENSOR_ACTIVE_S0,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &bmi160_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_ALS_GYRO,
+		.addr = BMI160_ADDR0,
+		.rot_standard_ref = NULL,
+		.default_range = 4, /* g, enough for laptop. */
+		.min_frequency = BMI160_ACCEL_MIN_FREQ,
+		.max_frequency = BMI160_ACCEL_MAX_FREQ,
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000,
+				.ec_rate = 76 * MSEC,
+			},
+		},
+	},
+
+	[LID_GYRO] = {
+		.name = "BMI160 GYRO",
+		.active_mask = SENSOR_ACTIVE_S0,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &bmi160_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_ALS_GYRO,
+		.addr = BMI160_ADDR0,
+		.rot_standard_ref = NULL,
+		.default_range = 1000, /* dps */
+		.min_frequency = BMI160_GYRO_MIN_FREQ,
+		.max_frequency = BMI160_GYRO_MAX_FREQ,
+	},
+
+	[LID_ALS] = {
+		.name = "Light",
+		.active_mask = SENSOR_ACTIVE_S0,
+		.chip = MOTIONSENSE_CHIP_OPT3001,
+		.type = MOTIONSENSE_TYPE_LIGHT,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &opt3001_drv,
+		.drv_data = &g_opt3001_data,
+		.port = I2C_PORT_ALS_GYRO,
+		.addr = OPT3001_I2C_ADDR,
+		.rot_standard_ref = NULL,
+		.default_range = 0x10000, /* scale = 1; uscale = 0 */
+		.min_frequency = OPT3001_LIGHT_MIN_FREQ,
+		.max_frequency = OPT3001_LIGHT_MAX_FREQ,
+		.config = {
+			/* Run ALS sensor in S0 */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 1000,
+			},
+		},
+	},
+
+	[VSYNC] = {
+		.name = "Camera VSYNC",
+		.active_mask = SENSOR_ACTIVE_S0,
+		.chip = MOTIONSENSE_CHIP_GPIO,
+		.type = MOTIONSENSE_TYPE_SYNC,
+		.location = MOTIONSENSE_LOC_CAMERA,
+		.drv = &sync_drv,
+		.default_range = 0,
+		.min_frequency = 0,
+		.max_frequency = 1,
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
+const struct motion_sensor_t *motion_als_sensors[] = {
+	&motion_sensors[LID_ALS],
+};
+BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
+
+const struct ppc_config_t ppc_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr = SN5S330_ADDR0,
+		.drv = &sn5s330_drv
+	},
+	{
+		.i2c_port = I2C_PORT_USB_C1,
+		.i2c_addr = SN5S330_ADDR0,
+		.drv = &sn5s330_drv,
+	},
+};
+const unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_COUNT] = {
+	{
+		.i2c_host_port = I2C_PORT_USB_C0,
+		.i2c_slave_addr = PS8751_I2C_ADDR1,
+		.drv = &tcpci_tcpm_drv,
+		.pol = TCPC_ALERT_ACTIVE_LOW,
+	},
+
+	{
+		.i2c_host_port = I2C_PORT_USB_C1,
+		.i2c_slave_addr = PS8751_I2C_ADDR1,
+		.drv = &tcpci_tcpm_drv,
+		.pol = TCPC_ALERT_ACTIVE_LOW,
+	},
+};
+
+/* The port_addr members are PD port numbers, not I2C port numbers. */
+struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_COUNT] = {
+	{
+		.port_addr = 0,
+		.driver = &tcpci_tcpm_usb_mux_driver,
+		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+	},
+
+	{
+		.port_addr = 1,
+		.driver = &tcpci_tcpm_usb_mux_driver,
+		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+	},
+};
+
+void board_chipset_startup(void)
+{
+	gpio_set_level(GPIO_EN_5V, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
+
+void board_chipset_shutdown(void)
+{
+	gpio_set_level(GPIO_EN_5V, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
+
+int board_get_version(void)
+{
+	static int board_version = -1;
+
+	if (board_version == -1) {
+		board_version = 0;
+		/* BRD_ID3 is LSb. */
+		if (gpio_get_level(GPIO_EC_BRD_ID3))
+			board_version |= 0x1;
+		if (gpio_get_level(GPIO_EC_BRD_ID2))
+			board_version |= 0x2;
+		if (gpio_get_level(GPIO_EC_BRD_ID1))
+			board_version |= 0x4;
+		if (gpio_get_level(GPIO_EC_BRD_ID0))
+			board_version |= 0x8;
+	}
+
+	return board_version;
+}
+
+static void board_init(void)
+{
+	/* Enable sensor interrupts. */
+	gpio_enable_interrupt(GPIO_ACCELGYRO3_INT_L);
+	gpio_enable_interrupt(GPIO_RCAM_VSYNC);
+
+	/* Enable USB Type-C interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void board_overcurrent_event(int port)
+{
+	/* Sanity check the port. */
+	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_COUNT))
+		return;
+
+	/* Note that the levels are inverted because the pin is active low. */
+	switch (port) {
+	case 0:
+		gpio_set_level(GPIO_USB_C0_OC_ODL, 0);
+		break;
+
+	case 1:
+		gpio_set_level(GPIO_USB_C1_OC_ODL, 0);
+		break;
+
+	default:
+		return;
+	};
+
+	/* TODO(b/69935262): Write a PD log entry for the OC event. */
+	CPRINTS("C%d: overcurrent!", port);
+}
+
+/*
+ * Check if PMIC fault registers indicate VR fault. If yes, print out fault
+ * register info to console. Additionally, set panic reason so that the OS can
+ * check for fault register info by looking at offset 0x14(PWRSTAT1) and
+ * 0x15(PWRSTAT2) in cros ec panicinfo.
+ */
+static void board_report_pmic_fault(const char *str)
+{
+	int vrfault, pwrstat1 = 0, pwrstat2 = 0;
+	uint32_t info;
+
+	/* RESETIRQ1 -- Bit 4: VRFAULT */
+	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, &vrfault)
+	    != EC_SUCCESS)
+		return;
+
+	if (!(vrfault & (1 << 4)))
+		return;
+
+	/* VRFAULT has occurred, print VRFAULT status bits. */
+
+	/* PWRSTAT1 */
+	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x16, &pwrstat1);
+
+	/* PWRSTAT2 */
+	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x17, &pwrstat2);
+
+	CPRINTS("PMIC VRFAULT: %s", str);
+	CPRINTS("PMIC VRFAULT: PWRSTAT1=0x%02x PWRSTAT2=0x%02x", pwrstat1,
+		pwrstat2);
+
+	/* Clear all faults -- Write 1 to clear. */
+	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, (1 << 4));
+	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x16, pwrstat1);
+	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x17, pwrstat2);
+
+	/*
+	 * Status of the fault registers can be checked in the OS by looking at
+	 * offset 0x14(PWRSTAT1) and 0x15(PWRSTAT2) in cros ec panicinfo.
+	 */
+	info = ((pwrstat2 & 0xFF) << 8) | (pwrstat1 & 0xFF);
+	panic_set_reason(PANIC_SW_PMIC_FAULT, info, 0);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/* GPIO_USB_PD_RST_L resets all the TCPCs. */
+	gpio_set_level(GPIO_USB_PD_RST_L, 0);
+	msleep(10); /* TODO(aaboagye): Verify min hold time. */
+	gpio_set_level(GPIO_USB_PD_RST_L, 1);
+}
+
+void board_rtc_reset(void)
+{
+	cprints(CC_CHIPSET, "Asserting RTCRST# to PCH");
+	gpio_set_level(GPIO_EC_PCH_RTCRST, 1);
+	udelay(100);
+	gpio_set_level(GPIO_EC_PCH_RTCRST, 0);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 &&
+			    port < CONFIG_USB_PD_PORT_COUNT);
+	int i;
+	int rv;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	CPRINTS("New chg p%d", port);
+
+	if (port == CHARGE_PORT_NONE) {
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			rv = ppc_vbus_sink_enable(i, 0);
+			/*
+			 * Deliberately ignoring this error since it may cause
+			 * an assertion error.
+			 */
+			if (rv)
+				CPRINTS("Disabling p%d sink path failed.", i);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTF("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTS("p%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTS("p%d: sink path enable failed.");
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+void board_set_charge_limit(int port, int supplier, int charge_ma,
+			    int max_ma, int charge_mv)
+{
+	charge_set_input_current_limit(MAX(charge_ma,
+					   CONFIG_CHARGER_INPUT_CURRENT),
+				       charge_mv);
+}
+
+static void board_chipset_reset(void)
+{
+	board_report_pmic_fault("CHIPSET RESET");
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESET, board_chipset_reset, HOOK_PRIO_DEFAULT);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and PPC.  Therefore, go
+	 * out and actually read the alert registers to report the alert status.
+	 */
+	if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+		/* The TCPCI spec says to ignore bits 14:12. */
+		regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+		if (regval)
+			status |= PD_STATUS_TCPC_ALERT_0;
+	}
+
+	if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+		/* TCPCI spec says to ignore bits 14:12. */
+		regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+		if (regval)
+			status |= PD_STATUS_TCPC_ALERT_1;
+	}
+
+	return status;
+}
diff --git a/board/nocturne/board.h b/board/nocturne/board.h
new file mode 100644
index 0000000000..0c9bfd9f1b
--- /dev/null
+++ b/board/nocturne/board.h
@@ -0,0 +1,240 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Nocturne board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* TODO(aaboagye): Remove before production. */
+#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands. */
+
+#define CONFIG_SUPPRESSED_HOST_COMMANDS \
+	EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_PD_GET_LOG_ENTRY
+
+/* NPCX7 config */
+#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
+#define NPCX_TACH_SEL2    0  /* No tach. */
+#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
+#define CONFIG_HIBERNATE_PSL
+
+/* Internal SPI flash on NPCX7 */
+#define CONFIG_FLASH_SIZE (512 * 1024) /* It's really 1MB. */
+#define CONFIG_SPI_FLASH_REGS
+#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
+
+/* EC modules */
+#define CONFIG_ADC
+#define CONFIG_BACKLIGHT_LID
+#define CONFIG_BOARD_VERSION_CUSTOM
+#define CONFIG_ESPI
+#define CONFIG_I2C
+#define CONFIG_I2C_MASTER
+#define CONFIG_LPC
+#define CONFIG_PWM
+#define CONFIG_VBOOT_HASH
+#define CONFIG_VSTORE
+#define CONFIG_VSTORE_SLOT_COUNT 1
+
+/* EC console commands */
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+#define CONFIG_CMD_BUTTON
+#define CONFIG_CMD_PD_CONTROL
+#define CONFIG_CMD_PPC_DUMP
+
+/* Battery */
+#define CONFIG_BATTERY_CUT_OFF
+#define CONFIG_BATTERY_SMART
+#define CONFIG_BATTERY_REVIVE_DISCONNECT
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_PRESENT_L
+
+/* Buttons / Switches */
+#define CONFIG_BUTTON_TRIGGERED_RECOVERY
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_VOLUME_BUTTONS
+
+/* Charger */
+#define CONFIG_CHARGE_MANAGER
+#define CONFIG_CHARGER
+#define CONFIG_CHARGER_DISCHARGE_ON_AC
+#define CONFIG_CHARGER_INPUT_CURRENT 128
+#define CONFIG_CHARGER_ISL9238
+#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
+#define CONFIG_CHARGER_V2
+#define CONFIG_EXTPOWER_GPIO
+
+/* LEDs */
+#define CONFIG_LED_COMMON
+#define CONFIG_LED_PWM_COUNT 2
+
+/* MKBP */
+#define CONFIG_MKBP_EVENT
+#define CONFIG_MKBP_USE_HOST_EVENT
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+
+/* Sensors */
+#define CONFIG_ALS
+#define ALS_COUNT 1
+#define CONFIG_ALS_OPT3001
+#define OPT3001_I2C_ADDR OPT3001_I2C_ADDR1
+#define CONFIG_ACCEL_FIFO 1024 /* Must be a power of 2 */
+/* Depends on how fast the AP boots and typical ODRs */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO / 3)
+#define CONFIG_ACCEL_INTERRUPTS
+#define CONFIG_ACCELGYRO_BMI160
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT TASK_EVENT_CUSTOM(4)
+#define CONFIG_SYNC
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_CUSTOM(8)
+
+/* SoC */
+#define CONFIG_BOARD_HAS_RTC_RESET
+#define CONFIG_CHIPSET_SKYLAKE
+#define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
+#define CONFIG_CHIPSET_RESET_HOOK
+#define CONFIG_POWER_COMMON
+#define CONFIG_POWER_BUTTON
+#define CONFIG_POWER_BUTTON_X86
+#define CONFIG_POWER_S0IX
+#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+
+/* USB PD */
+#define CONFIG_USB_PD_ALT_MODE
+#define CONFIG_USB_PD_ALT_MODE_DFP
+#define CONFIG_USB_PD_COMM_LOCKED
+#define CONFIG_USB_PD_DISCHARGE_PPC
+#define CONFIG_USB_PD_DUAL_ROLE
+#define CONFIG_USB_PD_LOGGING
+#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
+#define CONFIG_USB_PD_PORT_COUNT 2
+#define CONFIG_USB_PD_TCPM_PS8805
+#define CONFIG_USB_PD_TCPM_TCPCI
+#define CONFIG_USB_PD_TCPM_MUX
+#define CONFIG_USB_PD_TRY_SRC
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT
+#define CONFIG_USB_POWER_DELIVERY
+#define CONFIG_USBC_PPC_SN5S330
+#define CONFIG_USBC_SS_MUX
+#define CONFIG_USBC_SS_MUX_DFP_ONLY
+#define CONFIG_USBC_VCONN
+#define CONFIG_USBC_VCONN_SWAP
+
+/* Define typical operating power and max power. */
+#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_CURRENT_MA     3000
+#define PD_MAX_POWER_MW       45000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_VCONN_SWAP_DELAY   5000 /* us */
+
+/* TODO(aaboagye): Verify these timings. */
+/*
+ * delay to turn on the power supply max is ~16ms.
+ * delay to turn off the power supply max is about ~180ms.
+ */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY   30000  /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY  250000 /* us */
+
+/* I2C config */
+#define I2C_PORT_CHARGER  I2C_PORT_POWER
+#define I2C_PORT_PMIC     I2C_PORT_POWER
+#define I2C_PORT_POWER    NPCX_I2C_PORT0_0
+#define I2C_PORT_BATTERY  NPCX_I2C_PORT4_1
+#define I2C_PORT_ALS_GYRO NPCX_I2C_PORT5_0
+#define I2C_PORT_USB_C0   NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1   NPCX_I2C_PORT2_0
+
+#define GPIO_USB_C0_SCL GPIO_EC_I2C1_USB_C0_SCL
+#define GPIO_USB_C0_SDA GPIO_EC_I2C1_USB_C0_SDA
+#define GPIO_USB_C1_SCL GPIO_EC_I2C2_USB_C1_SCL
+#define GPIO_USB_C1_SDA GPIO_EC_I2C2_USB_C1_SDA
+
+#define I2C_ADDR_MP2949  0x40
+#define I2C_ADDR_BD99992 0x60
+
+/*
+ * Remapping of schematic GPIO names to common GPIO names expected (hardcoded)
+ * in the EC code base.
+ */
+#define GPIO_AC_PRESENT       GPIO_ACOK_OD
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_BL_DISABLE_ODL
+#define GPIO_BAT_PRESENT_L    GPIO_EC_BATT_PRES_L
+#define GPIO_ENTERING_RW      GPIO_EC_ENTERING_RW
+#define GPIO_PCH_PWRBTN_L     GPIO_EC_PCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L     GPIO_RSMRST_L
+#define GPIO_PCH_SLP_S0_L     GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L     GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L     GPIO_SLP_S4_L
+#define GPIO_PCH_SLP_SUS_L    GPIO_SLP_SUS_L_PCH
+#define GPIO_PCH_WAKE_L       GPIO_EC_PCH_WAKE_L
+#define GPIO_PMIC_DPWROK      GPIO_ROP_DSW_PWROK_EC
+#define GPIO_PMIC_SLP_SUS_L   GPIO_SLP_SUS_L_PMIC
+#define GPIO_POWER_BUTTON_L   GPIO_EC_PWR_BTN_IN_ODL
+#define GPIO_CPU_PROCHOT      GPIO_EC_PROCHOT_ODL
+#define GPIO_RSMRST_L_PGOOD   GPIO_ROP_EC_RSMRST_L
+#define GPIO_VOLUME_UP_L      GPIO_H1_EC_VOL_UP_ODL
+#define GPIO_VOLUME_DOWN_L    GPIO_H1_EC_VOL_DOWN_ODL
+#define GPIO_WP_L             GPIO_EC_WP_L
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+/* ADC signal */
+enum adc_channel {
+	ADC_BASE_ATTACH,
+	ADC_BASE_DETACH,
+	ADC_CH_COUNT
+};
+
+enum power_signal {
+	X86_SLP_S0_DEASSERTED,
+	X86_SLP_S3_DEASSERTED,
+	X86_SLP_S4_DEASSERTED,
+	X86_SLP_SUS_DEASSERTED,
+	X86_RSMRST_L_PGOOD,
+	X86_PMIC_DPWROK,
+	POWER_SIGNAL_COUNT
+};
+
+enum pwm_channel {
+	PWM_CH_DB0_LED_RED = 0,
+	PWM_CH_DB0_LED_GREEN,
+	PWM_CH_DB0_LED_BLUE,
+	PWM_CH_DB1_LED_RED,
+	PWM_CH_DB1_LED_GREEN,
+	PWM_CH_DB1_LED_BLUE,
+	PWM_CH_COUNT
+};
+
+/*
+ * Motion sensors:
+ * When reading through IO memory is set up for sensors (LPC is used),
+ * the first 2 entries must be accelerometers, then gyroscope.
+ * For BMI160, accel and gyro sensors must be next to each other.
+ */
+enum sensor_id {
+	LID_ACCEL,
+	LID_GYRO,
+	LID_ALS,
+	VSYNC,
+};
+
+#define CONFIG_ACCEL_FORCE_MODE_MASK (1 << LID_ALS)
+
+void base_pwr_fault_interrupt(enum gpio_signal s);
+int board_get_version(void);
+void board_rtc_reset(void);
+
+/* Reset all TCPCs. */
+void board_reset_pd_mcu(void);
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/nocturne/build.mk b/board/nocturne/build.mk
new file mode 100644
index 0000000000..1c2e1e04f2
--- /dev/null
+++ b/board/nocturne/build.mk
@@ -0,0 +1,13 @@
+# -*- makefile -*-
+# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m6f
+
+board-y=base_detect.o battery.o board.o led.o usb_pd_policy.o
diff --git a/board/nocturne/ec.tasklist b/board/nocturne/ec.tasklist
new file mode 100644
index 0000000000..46ba90a984
--- /dev/null
+++ b/board/nocturne/ec.tasklist
@@ -0,0 +1,33 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * List of enabled tasks in the priority order
+ *
+ * The first one has the lowest priority.
+ *
+ * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
+ * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
+ * where :
+ * 'n' in the name of the task
+ * 'r' in the main routine of the task
+ * 'd' in an opaque parameter passed to the routine at startup
+ * 's' is the stack size in bytes; must be a multiple of 8
+ *
+ * For USB PD tasks, IDs must be in consecutive order and correspond to
+ * the port which they are for. See TASK_ID_TO_PD_PORT() macro.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(PDCMD, pd_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/nocturne/gpio.inc b/board/nocturne/gpio.inc
new file mode 100644
index 0000000000..9e655c4a02
--- /dev/null
+++ b/board/nocturne/gpio.inc
@@ -0,0 +1,117 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first.
+ */
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_PD_INT_ODL,  PIN(6, 1), GPIO_INT_FALLING, usb_c_interrupt)
+GPIO_INT(USB_C1_PD_INT_ODL,  PIN(F, 5), GPIO_INT_FALLING, usb_c_interrupt)
+
+/* Power Sequencing interrupts */
+GPIO_INT(ROP_DSW_PWROK_EC,   PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(ROP_EC_RSMRST_L,    PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(EC_PWR_BTN_IN_ODL,  PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+GPIO_INT(SLP_S0_L,           PIN(A, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S4_L,           PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,           PIN(A, 6), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L_PCH,      PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(ACOK_OD,            PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)
+GPIO_INT(ROP_INT_L,          PIN(D, 5), GPIO_INT_BOTH | GPIO_PULL_UP, power_signal_interrupt)
+
+/* Misc. interrupts */
+GPIO_INT(H1_EC_VOL_DOWN_ODL, PIN(6, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(H1_EC_VOL_UP_ODL,   PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_WP_L,            PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(LID_OPEN,           PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(ACCELGYRO3_INT_L,   PIN(4, 1), GPIO_INT_FALLING, bmi160_interrupt)
+GPIO_INT(BASE_PWR_FAULT_ODL, PIN(2, 4), GPIO_INT_FALLING, base_pwr_fault_interrupt)
+GPIO_INT(RCAM_VSYNC,         PIN(E, 4), GPIO_INT_FALLING, sync_interrupt)
+
+/* SoC */
+GPIO(RSMRST_L,               PIN(C, 2), GPIO_OUT_LOW)
+GPIO(EC_PCH_PWR_BTN_L,       PIN(C, 1), GPIO_OUT_HIGH)
+GPIO(EC_PCH_RTCRST,          PIN(7, 6), GPIO_OUT_LOW)
+GPIO(SLP_SUS_L_PMIC,         PIN(D, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_L,          PIN(7, 4), GPIO_ODR_HIGH | GPIO_PULL_UP)
+GPIO(EC_PROCHOT_ODL,         PIN(3, 4), GPIO_ODR_HIGH)
+GPIO(SYS_RESET_L,            PIN(0, 2), GPIO_OUT_HIGH)
+GPIO(USB_C0_DP_HPD,          PIN(C, 5), GPIO_OUT_LOW)
+GPIO(USB_C1_DP_HPD,          PIN(C, 6), GPIO_OUT_LOW)
+
+/* Power Sequencing */
+GPIO(EC_PCH_ACPRESENT,       PIN(7, 3), GPIO_OUT_LOW)
+
+/* USB-C */
+GPIO(USB_C0_OC_ODL,          PIN(6, 7), GPIO_ODR_HIGH)
+GPIO(USB_C1_OC_ODL,          PIN(7, 0), GPIO_ODR_HIGH)
+GPIO(EN_5V,                  PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EN_USB_C0_3A,           PIN(6, 2), GPIO_OUT_LOW)
+GPIO(EN_USB_C1_3A,           PIN(8, 3), GPIO_OUT_LOW)
+
+/* Misc */
+GPIO(EC_BRD_ID0,             PIN(4, 0), GPIO_INPUT)
+GPIO(EC_BRD_ID1,             PIN(9, 6), GPIO_INPUT)
+GPIO(EC_BRD_ID2,             PIN(9, 3), GPIO_INPUT)
+GPIO(EC_BRD_ID3,             PIN(F, 0), GPIO_INPUT)
+GPIO(EC_GPIO95,              PIN(9, 5), GPIO_OUT_LOW)
+/* TODO(b/78640157): Determine what to do with this pin. */
+GPIO(UHALL_PWR_EN,           PIN(E, 0), GPIO_OUT_LOW)
+GPIO(USB2_VBUSSENSE,         PIN(A, 2), GPIO_OUT_LOW)
+GPIO(USB2_ID,                PIN(A, 0), GPIO_OUT_LOW)
+GPIO(USB_PD_RST_L,           PIN(F, 1), GPIO_OUT_HIGH)
+GPIO(ALS_INT_L,              PIN(5, 0), GPIO_INPUT)
+GPIO(CCD_MODE_ODL,           PIN(E, 3), GPIO_INPUT)
+GPIO(EC_BATT_PRES_L,         PIN(E, 5), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,         PIN(E, 1), GPIO_OUT_LOW)
+GPIO(EC_BL_DISABLE_ODL,      PIN(D, 3), GPIO_ODR_HIGH)
+GPIO(EC_PLATFORM_RST,        PIN(8, 6), GPIO_INPUT)
+GPIO(EC_GPIO31,              PIN(3, 1), GPIO_OUT_LOW)
+GPIO(BASE_PWR_EN,            PIN(2, 2), GPIO_OUT_LOW)
+GPIO(PP3300_NVME_EN,         PIN(2, 1), GPIO_OUT_LOW)
+GPIO(PP1800_NVME_EN,         PIN(2, 0), GPIO_OUT_LOW)
+GPIO(PPVAR_NVME_CORE_EN,     PIN(1, 7), GPIO_OUT_LOW)
+GPIO(EC_GPIO16,              PIN(1, 6), GPIO_OUT_LOW)
+GPIO(EC_GPIO15,              PIN(1, 5), GPIO_OUT_LOW)
+GPIO(EC_GPIO14,              PIN(1, 4), GPIO_OUT_LOW)
+
+/* I2C pins */
+GPIO(EC_I2C1_USB_C0_SCL,     PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C1_USB_C0_SDA,     PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C2_USB_C1_SCL,     PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C2_USB_C1_SDA,     PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C5_ALS_GYRO_SCL,   PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C5_ALS_GYRO_SDA,   PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C0_POWER_SCL,      PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C0_POWER_SDA,      PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C4_BATTERY_SCL,    PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C4_BATTERY_SDA,    PIN(F, 2), GPIO_INPUT)
+
+/* Alternate mode configuration */
+/* UART pins */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0) /* Cr50 requires no pullups. */
+/* I2C ports */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0) /* I2C0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0) /* I2C1 SDA */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0) /* I2C1 SCL, I2C 2 */
+ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0) /* I2C4 */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0) /* I2C5 */
+
+/* PWM */
+ALTERNATE(PIN_MASK(6, 0x01), 0, MODULE_PWM, 0) /* PWM7 */
+ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0) /* PWM3 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0) /* PWM5 */
+ALTERNATE(PIN_MASK(C, 0x31), 0, MODULE_PWM, 0) /* PWM0,2, 6 */
+
+/* ADC */
+ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0) /* ADC0,1 */
+
+/* Power Switch Logic (PSL) inputs */
+ALTERNATE(PIN_MASK(0, 0x03), 0, MODULE_PMU, 0) /* GPIO00, GPIO01 */
+ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0) /* GPIOD2 */
diff --git a/board/nocturne/led.c b/board/nocturne/led.c
new file mode 100644
index 0000000000..68b19f0bbe
--- /dev/null
+++ b/board/nocturne/led.c
@@ -0,0 +1,81 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Nocturne specific PWM LED settings. */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "led_pwm.h"
+#include "pwm.h"
+#include "util.h"
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_LEFT_LED,
+	EC_LED_ID_RIGHT_LED,
+};
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+/* We may not be using the blue channel long term. */
+struct pwm_led led_color_map[EC_LED_COLOR_COUNT] = {
+				/* Red, Green, Blue */
+	[EC_LED_COLOR_RED]    = {   1,   0,   0 },
+	[EC_LED_COLOR_GREEN]  = {   0,   1,   0 },
+	[EC_LED_COLOR_BLUE]   = {   0,   0,   0 },
+	[EC_LED_COLOR_YELLOW] = {   1,   1,   0 },
+	[EC_LED_COLOR_WHITE]  = {   0,   0,   0 },
+	[EC_LED_COLOR_AMBER]  = {  15,   1,   0 },
+};
+
+/* Two tri-color LEDs with red, green, and blue channels. */
+struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = {
+	{
+		PWM_CH_DB0_LED_RED,
+		PWM_CH_DB0_LED_GREEN,
+		PWM_CH_DB0_LED_BLUE,
+	},
+
+	{
+		PWM_CH_DB1_LED_RED,
+		PWM_CH_DB1_LED_GREEN,
+		PWM_CH_DB1_LED_BLUE,
+	},
+};
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_RED] = 100;
+	brightness_range[EC_LED_COLOR_GREEN] = 100;
+	brightness_range[EC_LED_COLOR_YELLOW] = 100;
+	brightness_range[EC_LED_COLOR_AMBER] = 100;
+	brightness_range[EC_LED_COLOR_BLUE] = 0;
+	brightness_range[EC_LED_COLOR_WHITE] = 0;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	enum pwm_led_id pwm_id;
+
+	/* Convert ec_led_id to pwm_led_id. */
+	if (led_id == EC_LED_ID_LEFT_LED)
+		pwm_id = PWM_LED0;
+	else if (led_id == EC_LED_ID_RIGHT_LED)
+		pwm_id = PWM_LED1;
+	else
+		return EC_ERROR_UNKNOWN;
+
+	if (brightness[EC_LED_COLOR_RED])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_RED);
+	else if (brightness[EC_LED_COLOR_GREEN])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_GREEN);
+	else if (brightness[EC_LED_COLOR_YELLOW])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_YELLOW);
+	else if (brightness[EC_LED_COLOR_AMBER])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
+	else
+		/* Otherwise, the "color" is "off". */
+		set_pwm_led_color(pwm_id, -1);
+
+	return EC_SUCCESS;
+}
diff --git a/board/nocturne/usb_pd_policy.c b/board/nocturne/usb_pd_policy.c
new file mode 100644
index 0000000000..684905fc83
--- /dev/null
+++ b/board/nocturne/usb_pd_policy.c
@@ -0,0 +1,422 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "common.h"
+#include "console.h"
+#include "compile_time_macros.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "system.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+
+#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_COMM_CAP|\
+			 PDO_FIXED_DATA_SWAP)
+
+const uint32_t pd_src_pdo[] = {
+		PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS),
+};
+const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
+
+const uint32_t pd_src_pdo_max[] = {
+	PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
+};
+const int pd_src_pdo_max_cnt = ARRAY_SIZE(pd_src_pdo_max);
+
+/* TODO(aaboagye): Determine correct values. */
+const uint32_t pd_snk_pdo[] = {
+		PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
+		PDO_BATT(4750, 21000, 15000),
+		PDO_VAR(4750, 21000, 3000),
+};
+const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
+
+int pd_board_checks(void)
+{
+	return EC_SUCCESS;
+}
+
+int pd_check_data_swap(int port, int data_role)
+{
+	/* Allow data swap if we are a UFP, otherwise don't allow. */
+	return (data_role == PD_ROLE_UFP) ? 1 : 0;
+}
+
+void pd_check_dr_role(int port, int dr_role, int flags)
+{
+	/* If UFP, try to switch to DFP */
+	if ((flags & PD_FLAGS_PARTNER_DR_DATA) &&
+			dr_role == PD_ROLE_UFP &&
+			system_get_image_copy() != SYSTEM_IMAGE_RO)
+		pd_request_data_swap(port);
+}
+
+/* TODO(aaboagye): re-eval for 3.0 & FRS. */
+int pd_check_power_swap(int port)
+{
+	/*
+	 * Allow power swap as long as we are acting as a dual role device,
+	 * otherwise assume our role is fixed (not in S0 or console command
+	 * to fix our role).
+	 */
+	return pd_get_dual_role() == PD_DRP_TOGGLE_ON ? 1 : 0;
+}
+
+void pd_check_pr_role(int port, int pr_role, int flags)
+{
+	/*
+	 * If partner is dual-role power and dualrole toggling is on, consider
+	 * if a power swap is necessary.
+	 */
+	if ((flags & PD_FLAGS_PARTNER_DR_POWER) &&
+	    pd_get_dual_role() == PD_DRP_TOGGLE_ON) {
+		/*
+		 * If we are a sink and partner is not externally powered, then
+		 * swap to become a source. If we are source and partner is
+		 * externally powered, swap to become a sink.
+		 */
+		int partner_extpower = flags & PD_FLAGS_PARTNER_EXTPOWER;
+
+		if ((!partner_extpower && pr_role == PD_ROLE_SINK) ||
+		     (partner_extpower && pr_role == PD_ROLE_SOURCE))
+			pd_request_power_swap(port);
+	}
+}
+
+int pd_check_vconn_swap(int port)
+{
+	/* Do not allow VCONN swap is 5V is off. */
+	return gpio_get_level(GPIO_EN_5V);
+}
+
+void pd_execute_data_swap(int port, int data_role)
+{
+	/* Do nothing */
+}
+
+int pd_is_valid_input_voltage(int mv)
+{
+	return 1;
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS. */
+	ppc_vbus_source_enable(port, 0);
+
+#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
+	/* Give back the current quota we are no longer using */
+	charge_manager_source_port(port, 0);
+#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= ppc_cnt)
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = ppc_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	/* Provide Vbus. */
+	rv = ppc_vbus_source_enable(port, 1);
+	if (rv)
+		return rv;
+
+#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
+	/* Ensure we advertise the proper available current quota */
+	charge_manager_source_port(port, 1);
+#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+void pd_transition_voltage(int idx)
+{
+	/* No-operation: we are always 5V */
+}
+
+void typec_set_source_current_limit(int p, int rp)
+{
+	ppc_set_vbus_source_current_limit(p, rp);
+}
+
+/* ----------------- Vendor Defined Messages ------------------ */
+const struct svdm_response svdm_rsp = {
+	.identity = NULL,
+	.svids = NULL,
+	.modes = NULL,
+};
+
+int pd_custom_vdm(int port, int cnt, uint32_t *payload,
+		  uint32_t **rpayload)
+{
+	int cmd = PD_VDO_CMD(payload[0]);
+	uint16_t dev_id = 0;
+	int is_rw, is_latest;
+
+	/* make sure we have some payload */
+	if (cnt == 0)
+		return 0;
+
+	switch (cmd) {
+	case VDO_CMD_VERSION:
+		/* guarantee last byte of payload is null character */
+		*(payload + cnt - 1) = 0;
+		CPRINTF("version: %s\n", (char *)(payload+1));
+		break;
+	case VDO_CMD_READ_INFO:
+	case VDO_CMD_SEND_INFO:
+		/* copy hash */
+		if (cnt == 7) {
+			dev_id = VDO_INFO_HW_DEV_ID(payload[6]);
+			is_rw = VDO_INFO_IS_RW(payload[6]);
+
+			is_latest = pd_dev_store_rw_hash(port,
+							 dev_id,
+							 payload + 1,
+							 is_rw ?
+							 SYSTEM_IMAGE_RW :
+							 SYSTEM_IMAGE_RO);
+
+			/*
+			 * Send update host event unless our RW hash is
+			 * already known to be the latest update RW.
+			 */
+			if (!is_rw || !is_latest)
+				pd_send_host_event(PD_EVENT_UPDATE_DEVICE);
+
+			CPRINTF("DevId:%d.%d SW:%d RW:%d\n",
+				HW_DEV_ID_MAJ(dev_id),
+				HW_DEV_ID_MIN(dev_id),
+				VDO_INFO_SW_DBG_VER(payload[6]),
+				is_rw);
+		} else if (cnt == 6) {
+			/* really old devices don't have last byte */
+			pd_dev_store_rw_hash(port, dev_id, payload + 1,
+					     SYSTEM_IMAGE_UNKNOWN);
+		}
+		break;
+	case VDO_CMD_CURRENT:
+		CPRINTF("Current: %dmA\n", payload[1]);
+		break;
+	case VDO_CMD_FLIP:
+		usb_mux_flip(port);
+		break;
+#ifdef CONFIG_USB_PD_LOGGING
+	case VDO_CMD_GET_LOG:
+		pd_log_recv_vdm(port, cnt, payload);
+		break;
+#endif /* CONFIG_USB_PD_LOGGING */
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_PD_ALT_MODE_DFP
+static int dp_flags[CONFIG_USB_PD_PORT_COUNT];
+static uint32_t dp_status[CONFIG_USB_PD_PORT_COUNT];
+
+static void svdm_safe_dp_mode(int port)
+{
+	/* make DP interface safe until configure */
+	dp_flags[port] = 0;
+	dp_status[port] = 0;
+	usb_mux_set(port, TYPEC_MUX_NONE,
+		USB_SWITCH_CONNECT, pd_get_polarity(port));
+}
+
+static int svdm_enter_dp_mode(int port, uint32_t mode_caps)
+{
+	/* Only enter mode if device is DFP_D capable */
+	if (mode_caps & MODE_DP_SNK) {
+		svdm_safe_dp_mode(port);
+		return 0;
+	}
+
+	return -1;
+}
+
+static int svdm_dp_status(int port, uint32_t *payload)
+{
+	int opos = pd_alt_mode(port, USB_SID_DISPLAYPORT);
+
+	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
+			 CMD_DP_STATUS | VDO_OPOS(opos));
+	payload[1] = VDO_DP_STATUS(0, /* HPD IRQ  ... not applicable */
+				   0, /* HPD level ... not applicable */
+				   0, /* exit DP? ... no */
+				   0, /* usb mode? ... no */
+				   0, /* multi-function ... no */
+				   (!!(dp_flags[port] & DP_FLAGS_DP_ON)),
+				   0, /* power low? ... no */
+				   (!!(dp_flags[port] & DP_FLAGS_DP_ON)));
+	return 2;
+};
+
+static int svdm_dp_config(int port, uint32_t *payload)
+{
+	int opos = pd_alt_mode(port, USB_SID_DISPLAYPORT);
+	int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
+	int pin_mode = pd_dfp_dp_get_pin_mode(port, dp_status[port]);
+
+	if (!pin_mode)
+		return 0;
+
+	usb_mux_set(port, mf_pref ? TYPEC_MUX_DOCK : TYPEC_MUX_DP,
+		    USB_SWITCH_CONNECT, pd_get_polarity(port));
+
+	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
+			 CMD_DP_CONFIG | VDO_OPOS(opos));
+	payload[1] = VDO_DP_CFG(pin_mode,      /* pin mode */
+				1,	       /* DPv1.3 signaling */
+				2);	       /* UFP connected */
+	return 2;
+};
+
+/*
+ * timestamp of the next possible toggle to ensure the 2-ms spacing
+ * between IRQ_HPD.
+ */
+static uint64_t hpd_deadline[CONFIG_USB_PD_PORT_COUNT];
+
+#define PORT_TO_HPD(port) ((port) ? GPIO_USB_C1_DP_HPD : GPIO_USB_C0_DP_HPD)
+
+static void svdm_dp_post_config(int port)
+{
+	const struct usb_mux *mux = &usb_muxes[port];
+
+	dp_flags[port] |= DP_FLAGS_DP_ON;
+	if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING))
+		return;
+
+	gpio_set_level(PORT_TO_HPD(port), 1);
+
+	/* set the minimum time delay (2ms) for the next HPD IRQ */
+	hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
+
+	mux->hpd_update(port, 1, 0);
+}
+
+static int svdm_dp_attention(int port, uint32_t *payload)
+{
+	int cur_lvl;
+	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
+	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
+	enum gpio_signal hpd = PORT_TO_HPD(port);
+	const struct usb_mux *mux = &usb_muxes[port];
+
+	cur_lvl = gpio_get_level(hpd);
+	dp_status[port] = payload[1];
+
+	/* Its initial DP status message prior to config */
+	if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
+		if (lvl)
+			dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
+		return 1;
+	}
+
+	if (irq & cur_lvl) {
+		uint64_t now = get_time().val;
+		/* wait for the minimum spacing between IRQ_HPD if needed */
+		if (now < hpd_deadline[port])
+			usleep(hpd_deadline[port] - now);
+
+		/* generate IRQ_HPD pulse */
+		gpio_set_level(hpd, 0);
+		usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
+		gpio_set_level(hpd, 1);
+
+		/* set the minimum time delay (2ms) for the next HPD IRQ */
+		hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
+	} else if (irq & !cur_lvl) {
+		CPRINTF("ERR:HPD:IRQ&LOW\n");
+		return 0; /* nak */
+	} else {
+		gpio_set_level(hpd, lvl);
+		/* set the minimum time delay (2ms) for the next HPD IRQ */
+		hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
+	}
+	mux->hpd_update(port, lvl, irq);
+	/* ack */
+	return 1;
+}
+
+static void svdm_exit_dp_mode(int port)
+{
+	const struct usb_mux *mux = &usb_muxes[port];
+
+	svdm_safe_dp_mode(port);
+	gpio_set_level(PORT_TO_HPD(port), 0);
+	mux->hpd_update(port, 0, 0);
+}
+
+static int svdm_enter_gfu_mode(int port, uint32_t mode_caps)
+{
+	/* Always enter GFU mode */
+	return 0;
+}
+
+static void svdm_exit_gfu_mode(int port)
+{
+}
+
+static int svdm_gfu_status(int port, uint32_t *payload)
+{
+	/*
+	 * This is called after enter mode is successful, send unstructured
+	 * VDM to read info.
+	 */
+	pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_READ_INFO, NULL, 0);
+	return 0;
+}
+
+static int svdm_gfu_config(int port, uint32_t *payload)
+{
+	return 0;
+}
+
+static int svdm_gfu_attention(int port, uint32_t *payload)
+{
+	return 0;
+}
+
+const struct svdm_amode_fx supported_modes[] = {
+	{
+		.svid = USB_SID_DISPLAYPORT,
+		.enter = &svdm_enter_dp_mode,
+		.status = &svdm_dp_status,
+		.config = &svdm_dp_config,
+		.post_config = &svdm_dp_post_config,
+		.attention = &svdm_dp_attention,
+		.exit = &svdm_exit_dp_mode,
+	},
+	{
+		.svid = USB_VID_GOOGLE,
+		.enter = &svdm_enter_gfu_mode,
+		.status = &svdm_gfu_status,
+		.config = &svdm_gfu_config,
+		.attention = &svdm_gfu_attention,
+		.exit = &svdm_exit_gfu_mode,
+	}
+};
+const int supported_modes_cnt = ARRAY_SIZE(supported_modes);
+#endif /* CONFIG_USB_PD_ALT_MODE_DFP */