Intel GLK-RVP: Add initial board bringup code

Added bare minimum code to bringup the Intel GLK-RVP using
Nuvoton AIC.

BUG=b:64394037
BRANCH=glkrvp
TEST=Intel GLK-RVP2.0 boots to Chrome OS using Nuvoton AIC.

Change-Id: I86816d09fe428091438a16f014e23b2e0c0025b7
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/602515
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>

5 files changed, 432 insertions, 0 deletions

diff --git a/board/glkrvp/board.c b/board/glkrvp/board.c
new file mode 100644
index 0000000000..75cef56640
--- /dev/null
+++ b/board/glkrvp/board.c
@@ -0,0 +1,124 @@
+/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel GLK-RVP board-specific configuration */
+
+#include "chipset.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "spi.h"
+#include "switch.h"
+#include "system.h"
+#include "task.h"
+#include "timer.h"
+#include "uart.h"
+#include "util.h"
+
+#include "gpio_list.h"
+
+/* power signal list.  Must match order of enum power_signal. */
+const struct power_signal_info power_signal_list[] = {
+	{GPIO_RSMRST_L_PGOOD,     1, "RSMRST_L"},
+	{GPIO_PCH_SLP_S3_L,       1, "SLP_S3_DEASSERTED"},
+	{GPIO_PCH_SLP_S4_L,       1, "SLP_S4_DEASSERTED"},
+
+	{GPIO_ALL_SYS_PGOOD,      1, "ALL_SYS_PGOOD"},
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	{"master0-0", NPCX_I2C_PORT0_0, 400, GPIO_I2C0_SCL0, GPIO_I2C0_SDA0},
+	{"master0-1", NPCX_I2C_PORT0_1, 400, GPIO_I2C0_SCL1, GPIO_I2C0_SDA1},
+	{"master1",   NPCX_I2C_PORT1,   400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
+	{"master2",   NPCX_I2C_PORT2,   100, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
+	{"master3",   NPCX_I2C_PORT3,   100, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/* Wake-up pins for hibernate */
+const enum gpio_signal hibernate_wake_pins[] = {
+	GPIO_POWER_BUTTON_L,
+};
+
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
+
+/* Called by APL power state machine when transitioning from G3 to S5 */
+static void chipset_pre_init(void)
+{
+	/*
+	 * No need to re-init PMIC since settings are sticky across sysjump.
+	 * However, be sure to check that PMIC is already enabled. If it is
+	 * then there's no need to re-sequence the PMIC.
+	 */
+	if (system_jumped_to_this_image())
+		return;
+
+	/* TODO: Enable PMIC */
+}
+DECLARE_HOOK(HOOK_CHIPSET_PRE_INIT, chipset_pre_init, HOOK_PRIO_DEFAULT);
+
+
+/* Initialize board. */
+static void board_init(void)
+{
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_FIRST);
+
+/* Called on AP S5 -> S3 transition */
+static void board_chipset_startup(void)
+{
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S3 -> S5 transition */
+static void board_chipset_shutdown(void)
+{
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
+
+void chipset_do_shutdown(void)
+{
+	/* TODO: Disable PMIC */
+	/* gpio_set_level(GPIO_PMIC_EN, 0); */
+}
+
+void board_hibernate_late(void)
+{
+}
+
+void board_hibernate(void)
+{
+	/*
+	 * To support hibernate called from console commands, ectool commands
+	 * and key sequence, shutdown the AP before hibernating.
+	 */
+	chipset_do_shutdown();
+
+	/* Added delay to allow AP to settle down */
+	msleep(100);
+}
+
+int charge_prevent_power_on(int power_button_pressed)
+{
+	return 0;
+}
+
+int extpower_is_present(void)
+{
+	return 1;
+}
+
+int charge_want_shutdown(void)
+{
+	return 0;
+}
diff --git a/board/glkrvp/board.h b/board/glkrvp/board.h
new file mode 100644
index 0000000000..77c45d7cc5
--- /dev/null
+++ b/board/glkrvp/board.h
@@ -0,0 +1,102 @@
+/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel GLK-RVP board-specific configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/*
+ * Allow dangerous commands.
+ * TODO: Remove this config before production.
+ */
+#define CONFIG_SYSTEM_UNLOCKED
+
+#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#undef CONFIG_HOSTCMD_DEBUG_MODE
+
+/*
+ * By default, enable all console messages excepted HC, ACPI and event:
+ * The sensor stack is generating a lot of activity.
+ */
+#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
+
+/* EC console commands  */
+
+/* Battery */
+
+/* Charger */
+
+/* Keyboard */
+#define CONFIG_KEYBOARD_PROTOCOL_8042
+
+/* UART */
+#define NPCX_UART_MODULE2    1 /* 0:GPIO10/11 1:GPIO64/65 as UART */
+
+/* USB-A config */
+
+/* USB PD config */
+
+/* SoC / PCH */
+#define CONFIG_LPC
+#define CONFIG_CHIPSET_APOLLOLAKE
+#define CONFIG_CHIPSET_RESET_HOOK
+#define CONFIG_POWER_BUTTON
+#define CONFIG_POWER_BUTTON_X86
+#define CONFIG_POWER_COMMON
+
+/* EC */
+#define CONFIG_WP_ALWAYS
+#define CONFIG_I2C
+#define CONFIG_I2C_MASTER
+
+#define CONFIG_LID_SWITCH
+#define CONFIG_LTO
+#define CONFIG_UART_HOST 0
+
+#define CONFIG_FLASH_SIZE 524288
+#define CONFIG_SPI_FLASH_REGS
+#define CONFIG_SPI_FLASH_W25Q40
+
+/*
+ * Enable 1 slot of secure temporary storage to support
+ * suspend/resume with read/write memory training.
+ */
+#define CONFIG_VSTORE
+#define CONFIG_VSTORE_SLOT_COUNT 1
+
+/* Optional feature - used by nuvoton */
+#define NPCX_JTAG_MODULE2    0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
+#define NPCX_TACH_SEL2       0 /* 0:GPIO40/A4 1:GPIO93/D3 as TACH */
+
+/* I2C ports */
+
+/* EC exclude modules */
+#undef CONFIG_ADC
+#undef CONFIG_PECI
+#undef CONFIG_SWITCH
+#undef CONFIG_WATCHDOG
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum power_signal {
+	X86_RSMRST_N = 0,
+	X86_SLP_S3_N,
+	X86_SLP_S4_N,
+
+	X86_ALL_SYS_PG,		/* PMIC_EC_PWROK_OD */
+
+	/* Number of X86 signals */
+	POWER_SIGNAL_COUNT
+};
+
+/* Define typical operating power and max power */
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/glkrvp/build.mk b/board/glkrvp/build.mk
new file mode 100644
index 0000000000..ea148af8f4
--- /dev/null
+++ b/board/glkrvp/build.mk
@@ -0,0 +1,12 @@
+# -*- makefile -*-
+# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_VARIANT:=npcx5m6g
+
+board-y=board.o
diff --git a/board/glkrvp/ec.tasklist b/board/glkrvp/ec.tasklist
new file mode 100644
index 0000000000..2c401f93e2
--- /dev/null
+++ b/board/glkrvp/ec.tasklist
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel RVP board-specific configuration */
+
+/*
+ * List of enabled tasks in the priority order
+ *
+ * The first one has the lowest priority.
+ *
+ * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
+ * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
+ * where :
+ * 'n' in the name of the task
+ * 'r' in the main routine of the task
+ * 'd' in an opaque parameter passed to the routine at startup
+ * 's' is the stack size in bytes; must be a multiple of 8
+ *
+ * For USB PD tasks, IDs must be in consecutive order and correspond to
+ * the port which they are for. See TASK_ID_TO_PD_PORT() macro.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)
diff --git a/board/glkrvp/gpio.inc b/board/glkrvp/gpio.inc
new file mode 100644
index 0000000000..b5c58eaf2a
--- /dev/null
+++ b/board/glkrvp/gpio.inc
@@ -0,0 +1,161 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel GLK-RVP board-specific configuration */
+
+/*
+ * Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first.
+ */
+GPIO_INT(PCH_SLP_S4_L,		PIN(8, 6), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S4_L */
+GPIO_INT(PCH_SLP_S3_L,		PIN(8, 5), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S3_L */
+GPIO_INT(RSMRST_L_PGOOD,	PIN(3, 6), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_RSMRST_ODL */
+GPIO_INT(ALL_SYS_PGOOD,		PIN(7, 2), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_PWROK_ODL */
+GPIO_INT(POWER_BUTTON_L,	PIN(A, 6), GPIO_INT_BOTH, power_button_interrupt)	/* MECH_PWR_BTN_ODL */
+GPIO_INT(LID_OPEN,		PIN(0, 3), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt)	/* SMC_LID */
+
+GPIO(PCH_SMI_L,		PIN(C, 6), GPIO_ODR_HIGH)		/* EC_SMI_ODL */
+GPIO(PCH_SCI_L,		PIN(7, 6), GPIO_ODR_HIGH)		/* EC_SCI_ODL */
+GPIO(PCH_PWRBTN_L,	PIN(7, 5), GPIO_ODR_HIGH)		/* EC_PCH_PWR_BTN_ODL */
+GPIO(PCH_WAKE_L,	PIN(7, 0), GPIO_ODR_HIGH)		/* EC_PCH_WAKE_ODL */
+GPIO(PCH_SYS_PWROK,	PIN(3, 5), GPIO_OUT_LOW)		/* EC_PCH_PWROK */
+GPIO(ENABLE_BACKLIGHT,	PIN(9, 7), GPIO_ODR_HIGH)		/* EC_BL_EN_OD */
+GPIO(ENTERING_RW,	PIN(A, 7), GPIO_OUTPUT)			/* EC_ENTERING_RW */
+
+GPIO(PCH_RSMRST_L,	PIN(0, 1), GPIO_OUT_LOW)		/* EC_PCH_RSMRST_L */
+GPIO(PCH_RCIN_L,	PIN(0, 0), GPIO_ODR_HIGH)		/* SYS_RST_ODL */
+GPIO(PCH_SLP_S0_L,	PIN(8, 1), GPIO_INPUT)			/* SLP_S0_L */
+GPIO(SMC_SHUTDOWN,	PIN(3, 3), GPIO_OUT_LOW | GPIO_PULL_DOWN)	/* A_RAIL_EN */
+
+/*
+ * PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is
+ * normally driven by the PMIC. The EC can also drive this signal in the event
+ * that the ambient or charger temperature sensors exceeds their thresholds.
+ */
+GPIO(CPU_PROCHOT,	PIN(A, 3), GPIO_INPUT)			/* PCH_PROCHOT_ODL */
+GPIO(EC_PCH_RTCRST,	PIN(B, 7), GPIO_INPUT)			/* EC_PCH_RTCRST TODO: Not used yet */
+
+/*
+ * I2C pins should be configured as inputs until I2C module is
+ * initialized. This will avoid driving the lines unintentionally.
+ */
+GPIO(I2C0_SCL0,     PIN(B, 5), GPIO_ODR_HIGH)
+GPIO(I2C0_SDA0,     PIN(B, 4), GPIO_ODR_HIGH)
+GPIO(I2C0_SCL1,     PIN(B, 3), GPIO_ODR_HIGH)
+GPIO(I2C0_SDA1,     PIN(B, 2), GPIO_ODR_HIGH)
+GPIO(I2C1_SCL,      PIN(9, 0), GPIO_ODR_HIGH)
+GPIO(I2C1_SDA,      PIN(8, 7), GPIO_ODR_HIGH)
+GPIO(I2C2_SCL,      PIN(9, 2), GPIO_ODR_HIGH)
+GPIO(I2C2_SDA,      PIN(9, 1), GPIO_ODR_HIGH)
+GPIO(I2C3_SCL,      PIN(D, 1), GPIO_ODR_HIGH)
+GPIO(I2C3_SDA,      PIN(D, 0), GPIO_ODR_HIGH)
+
+/* Unused pins 3.3V & Interruptable */
+GPIO(NC_02,	PIN(0, 2), GPIO_INPUT)
+GPIO(NC_04,	PIN(0, 4), GPIO_INPUT)
+
+GPIO(NC_34,	PIN(3, 4), GPIO_INPUT)
+GPIO(NC_37,	PIN(3, 7), GPIO_INPUT)
+
+GPIO(NC_41,	PIN(4, 1), GPIO_INPUT)
+GPIO(NC_42,	PIN(4, 2), GPIO_INPUT)
+
+GPIO(NC_60,	PIN(6, 0), GPIO_INPUT)
+GPIO(NC_62,	PIN(6, 2), GPIO_INPUT)
+GPIO(NC_63,	PIN(6, 3), GPIO_INPUT)
+
+GPIO(NC_71,	PIN(7, 1), GPIO_INPUT)
+GPIO(NC_73,	PIN(7, 3), GPIO_INPUT)
+GPIO(NC_74,	PIN(7, 4), GPIO_INPUT)
+
+GPIO(NC_80,	PIN(8, 0), GPIO_INPUT)
+GPIO(NC_82,	PIN(8, 2), GPIO_INPUT)
+GPIO(NC_83,	PIN(8, 3), GPIO_INPUT)
+GPIO(NC_84,	PIN(8, 4), GPIO_INPUT)
+
+GPIO(NC_B1,	PIN(B, 1), GPIO_INPUT)
+
+GPIO(NC_C0,	PIN(C, 0), GPIO_INPUT)
+GPIO(NC_C1,	PIN(C, 1), GPIO_INPUT)
+GPIO(NC_C2,	PIN(C, 2), GPIO_INPUT)
+GPIO(NC_C3,	PIN(C, 3), GPIO_INPUT)
+GPIO(NC_C4,	PIN(C, 4), GPIO_INPUT)
+GPIO(NC_C5,	PIN(C, 5), GPIO_INPUT)
+GPIO(NC_C7,	PIN(C, 7), GPIO_INPUT)
+
+GPIO(NC_D2,	PIN(D, 2), GPIO_INPUT)
+GPIO(NC_D3,	PIN(D, 3), GPIO_INPUT)
+
+GPIO(NC_E7,	PIN(E, 7), GPIO_INPUT)
+
+/* Unused pins: VSPI 3.3V or 1.8V & Interruptable */
+GPIO(NC_93,	PIN(9, 3), GPIO_INPUT)
+GPIO(NC_94,	PIN(9, 4), GPIO_INPUT)
+GPIO(NC_95,	PIN(9, 5), GPIO_INPUT)
+
+GPIO(NC_A1,	PIN(A, 1), GPIO_INPUT)
+GPIO(NC_A5,	PIN(A, 5), GPIO_INPUT)
+
+GPIO(NC_B0,	PIN(B, 0), GPIO_INPUT)
+
+/* Unused pins 3.3V & Non-Interruptable */
+GPIO(NC_32,	PIN(3, 2), GPIO_INPUT)
+
+GPIO(NC_66,	PIN(6, 6), GPIO_INPUT)
+
+GPIO(NC_B6,	PIN(B, 6), GPIO_INPUT)
+
+/* eSPI: VHIF Unused pins 1.8V & Interruptable */
+GPIO(NC_46,	PIN(4, 6), GPIO_INPUT)
+GPIO(NC_47,	PIN(4, 7), GPIO_INPUT)
+
+GPIO(NC_50,	PIN(5, 0), GPIO_INPUT)
+GPIO(NC_51,	PIN(5, 1), GPIO_INPUT)
+GPIO(NC_52,	PIN(5, 2), GPIO_INPUT)
+GPIO(NC_53,	PIN(5, 3), GPIO_INPUT)
+GPIO(NC_54,	PIN(5, 4), GPIO_INPUT)
+GPIO(NC_55,	PIN(5, 5), GPIO_INPUT)
+GPIO(NC_56,	PIN(5, 6), GPIO_INPUT)
+GPIO(NC_57,	PIN(5, 7), GPIO_INPUT)
+
+/* Alternate pins for UART */
+ALTERNATE(PIN_MASK(6, 0x30), 1,  MODULE_UART,        0)    /* GPIO64/65    */
+
+/* Alternate pins for I2C */
+ALTERNATE(PIN_MASK(B, 0x0C), 1,  MODULE_I2C,         0)    /* I2C0SDA1/I2C0SCL1       GPIOB2/B3	   */
+ALTERNATE(PIN_MASK(B, 0x30), 1,  MODULE_I2C,         0)    /* I2C0SDA0/I2C0SCL0       GPIOB4/B5	   */
+ALTERNATE(PIN_MASK(8, 0x80), 1,  MODULE_I2C,         0)    /* I2C1SDA                 GPIO87       */
+ALTERNATE(PIN_MASK(9, 0x07), 1,  MODULE_I2C,         0)    /* I2C1SCL/I2C2SDA/I2C2SCL GPIO90/91/92 */
+ALTERNATE(PIN_MASK(D, 0x03), 1,  MODULE_I2C,         0)    /* I2C3SDA/I2C3SCL         GPIOD0/D1    */
+
+/* Alternate pins for ADC/SPI/PWM/MFT */
+ALTERNATE(PIN_MASK(4, 0x38), 1,  MODULE_ADC,         0)    /* ADC                     GPIO45/44/43 */
+ALTERNATE(PIN_MASK(A, 0x0A), 1,  MODULE_SPI,         0)    /* SPIP_MOSI/SPIP_SCLK     GPIOA3/A1	   */
+ALTERNATE(PIN_MASK(9, 0x20), 1,  MODULE_SPI,         0)    /* SPIP_MISO               GPIO95       */
+ALTERNATE(PIN_MASK(C, 0x04), 3,  MODULE_PWM,         0)    /* PWM1 for PWM/KBLIGHT Test GPIOC2     */
+/* Alternative functionality for FANS */
+#ifdef CONFIG_FANS
+ALTERNATE(PIN_MASK(C, 0x08), 7,  MODULE_PWM,         0)    /* PWM0 for PWM/FAN Test   GPIOC3       */
+#if NPCX_TACH_SEL2
+ALTERNATE(PIN_MASK(9, 0x08), 3,  MODULE_PWM,         0)    /* MFT-1/TA1_TACH1 for FAN GPIO93       */
+#else
+ALTERNATE(PIN_MASK(4, 0x01), 3,  MODULE_PWM,         0)    /* MFT-1/TA1_TACH1 for FAN Test GPIO40  */
+#endif
+#endif
+
+/* Keyboard pins */
+#define GPIO_KB_INPUT (GPIO_INPUT)
+#define GPIO_KB_OUTPUT (GPIO_ODR_HIGH)
+
+/* Keyboard Columns */
+ALTERNATE(PIN_MASK(0, 0xE0), 0,  MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT) /* GPIO05/06/07 */
+ALTERNATE(PIN_MASK(1, 0xFF), 0,  MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT) /* GPIO10/11/12/13/14/15/16/17 */
+ALTERNATE(PIN_MASK(2, 0x03), 0,  MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT) /* GPIO20/21 */
+
+/* Keyboard Rows */
+ALTERNATE(PIN_MASK(2, 0xFC), 0,  MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* GPIO22/23/24/25/26/27 */
+ALTERNATE(PIN_MASK(3, 0x03), 0,  MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* GPIO30/31 */