diff options
| author | Caveh Jalali <caveh@chromium.org> | 2018-06-04 18:35:10 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-06-05 02:15:30 -0700 |
| commit | 8f21950cc04811865383f25c24557226568e3c70 (patch) | |
| tree | f6c41a8db36b96f951a70f7cc129b1b0f6d0713f /board | |
| parent | 2e49341d31b292e977327a07cc5b14b212e4a1ba (diff) | |
| download | chrome-ec-8f21950cc04811865383f25c24557226568e3c70.tar.gz | |
atlas: config PCH_PWR_BTN as push-pull
we don't have a pullup on PCH_PWR_BTN, so just configure it as
push-pull.
BUG=b:78309559
BRANCH=none
TEST=able to power down/up the AP
Change-Id: I791bfe3fb1c168ac72762f748f744cfbe771169b
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1086470
Commit-Ready: caveh jalali <caveh@chromium.org>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/atlas/board.h | 2 | ||||
| -rw-r--r-- | board/atlas/gpio.inc | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/board/atlas/board.h b/board/atlas/board.h index 2a3ee997f8..b800e99909 100644 --- a/board/atlas/board.h +++ b/board/atlas/board.h @@ -251,7 +251,7 @@ void board_reset_pd_mcu(void); #define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW #define GPIO_KBD_KSO2 GPIO_EC_KB_ROW02_INV #define GPIO_PCH_ACOK GPIO_EC_PCH_ACPRESENT -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_L #define GPIO_PCH_RSMRST_L GPIO_RSMRST_L #define GPIO_PCH_SLP_SUS_L GPIO_SLP_SUS_L_PCH #define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_L diff --git a/board/atlas/gpio.inc b/board/atlas/gpio.inc index 86c40abd90..1d4777bcb1 100644 --- a/board/atlas/gpio.inc +++ b/board/atlas/gpio.inc @@ -27,7 +27,7 @@ GPIO_INT(ACCELGYRO3_INT_L, PIN(4, 1), GPIO_INT_FALLING, bmi160_interrupt) /* SoC section */ GPIO(RSMRST_L, PIN(3, 7), GPIO_OUT_LOW) /* SOC Resume Reset */ -GPIO(EC_PCH_PWR_BTN_ODL, PIN(C, 1), GPIO_ODR_HIGH) /* Power button to SOC */ +GPIO(EC_PCH_PWR_BTN_L, PIN(C, 1), GPIO_OUT_HIGH) /* Power button to SOC */ GPIO(EC_PCH_RTCRST, PIN(7, 6), GPIO_OUT_LOW) /* RTC Reset (broken) */ GPIO(EC_PCH_WAKE_L, PIN(7, 4), GPIO_ODR_HIGH) /* PCH wake */ GPIO(EC_PROCHOT_ODL, PIN(3, 4), GPIO_INPUT) /* SOC PROCHOT# */ |