common: replace 1 << digits, with BIT(digits)

Requested for linux integration, use BIT instead of 1 <<
First step replace bit operation with operand containing only digits.

Fix an error in motion_lid try to set bit 31 of a signed integer.

BUG=None
BRANCH=None
TEST=compile

Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518659
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>

49 files changed, 169 insertions, 169 deletions

diff --git a/board/atlas/board.c b/board/atlas/board.c
index 3be1ebfb3d..e0fc4d07e7 100644
--- a/board/atlas/board.c
+++ b/board/atlas/board.c
@@ -274,7 +274,7 @@ static void board_report_pmic_fault(const char *str)
 		      BD99992GW_REG_RESETIRQ1, &vrfault) != EC_SUCCESS)
 		return;
 
-	if (!(vrfault & (1 << 4)))
+	if (!(vrfault & BIT(4)))
 		return;
 
 	/* VRFAULT has occurred, print VRFAULT status bits. */
@@ -293,7 +293,7 @@ static void board_report_pmic_fault(const char *str)
 
 	/* Clear all faults -- Write 1 to clear. */
 	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992,
-		   BD99992GW_REG_RESETIRQ1, (1 << 4));
+		   BD99992GW_REG_RESETIRQ1, BIT(4));
 	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992,
 		   BD99992GW_REG_PWRSTAT1, pwrstat1);
 	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992,
diff --git a/board/coffeecake/board.c b/board/coffeecake/board.c
index bddfb0d159..e00c9e7b4b 100644
--- a/board/coffeecake/board.c
+++ b/board/coffeecake/board.c
@@ -140,15 +140,15 @@ void board_set_usb_output_voltage(int mv)
 void board_config_pre_init(void)
 {
 	/* Enable SYSCFG clock */
-	STM32_RCC_APB2ENR |= 1 << 0;
+	STM32_RCC_APB2ENR |= BIT(0);
 	/* Enable DAC interface clock. */
-	STM32_RCC_APB1ENR |= (1 << 29);
+	STM32_RCC_APB1ENR |= BIT(29);
 	/* Delay 1 APB clock cycle after the clock is enabled */
 	clock_wait_bus_cycles(BUS_APB, 1);
 	/* Set 5Vsafe Vdac */
 	board_set_usb_output_voltage(5000);
 	/* Remap USART DMA to match the USART driver */
-	STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10);/* Remap USART1 RX/TX DMA */
+	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10);/* Remap USART1 RX/TX DMA */
 }
 
 #ifdef CONFIG_SPI_FLASH
@@ -156,7 +156,7 @@ void board_config_pre_init(void)
 static void board_init_spi2(void)
 {
 	/* Remap SPI2 to DMA channels 6 and 7 */
-	STM32_SYSCFG_CFGR1 |= (1 << 24);
+	STM32_SYSCFG_CFGR1 |= BIT(24);
 
 	/* Set pin NSS to general purpose output mode (01b). */
 	/* Set pins SCK, MISO, and MOSI to alternate function (10b). */
@@ -176,8 +176,8 @@ static void board_init_spi2(void)
 	STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
 
 	/* Reset SPI2 */
-	STM32_RCC_APB1RSTR |= (1 << 14);
-	STM32_RCC_APB1RSTR &= ~(1 << 14);
+	STM32_RCC_APB1RSTR |= BIT(14);
+	STM32_RCC_APB1RSTR &= ~BIT(14);
 
 	/* Enable clocks to SPI2 module */
 	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
diff --git a/board/coffeecake/usb_pd_config.h b/board/coffeecake/usb_pd_config.h
index 2282ea4e4b..e2c1dbb2db 100644
--- a/board/coffeecake/usb_pd_config.h
+++ b/board/coffeecake/usb_pd_config.h
@@ -50,7 +50,7 @@ static inline void spi_enable_clock(int port)
 #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
 #define TIM_CCR_CS  1
-#define EXTI_COMP_MASK(p) (1 << 21)
+#define EXTI_COMP_MASK(p) BIT(21)
 #define IRQ_COMP STM32_IRQ_COMP
 /* triggers packet detection on comparator falling edge */
 #define EXTI_XTSR STM32_EXTI_FTSR
@@ -71,8 +71,8 @@ static inline void pd_set_pins_speed(int port)
 static inline void pd_tx_spi_reset(int port)
 {
 	/* Reset SPI1 */
-	STM32_RCC_APB2RSTR |= (1 << 12);
-	STM32_RCC_APB2RSTR &= ~(1 << 12);
+	STM32_RCC_APB2RSTR |= BIT(12);
+	STM32_RCC_APB2RSTR &= ~BIT(12);
 }
 
 /* Drive the CC line from the TX block */
diff --git a/board/cr50/rdd.c b/board/cr50/rdd.c
index 8128d1b24c..876ba5dcef 100644
--- a/board/cr50/rdd.c
+++ b/board/cr50/rdd.c
@@ -34,15 +34,15 @@ enum ccd_block_flags {
 	 * UARTs.  Disabling these can be helpful if the AP or EC is doing
 	 * something which creates an interrupt storm on these ports.
 	 */
-	CCD_BLOCK_AP_UART = (1 << 0),
-	CCD_BLOCK_EC_UART = (1 << 1),
+	CCD_BLOCK_AP_UART = BIT(0),
+	CCD_BLOCK_EC_UART = BIT(1),
 
 	/*
 	 * Any ports shared with servo.  Disabling these will stop CCD from
 	 * interfering with servo, in the case where both CCD and servo is
 	 * connected but servo isn't properly detected.
 	 */
-	CCD_BLOCK_SERVO_SHARED = (1 << 2)
+	CCD_BLOCK_SERVO_SHARED = BIT(2)
 };
 
 /* Which UARTs are blocked by console command */
@@ -128,28 +128,28 @@ enum ccd_state_flag {
 	/* Flags for individual devices/ports */
 
 	/* AP UART is enabled.  RX-only, unless TX is also enabled. */
-	CCD_ENABLE_UART_AP		= (1 << 0),
+	CCD_ENABLE_UART_AP		= BIT(0),
 
 	/* AP UART transmit is enabled.  Requires AP UART enabled. */
-	CCD_ENABLE_UART_AP_TX		= (1 << 1),
+	CCD_ENABLE_UART_AP_TX		= BIT(1),
 
 	/* EC UART is enabled.  RX-only, unless TX is also enabled. */
-	CCD_ENABLE_UART_EC		= (1 << 2),
+	CCD_ENABLE_UART_EC		= BIT(2),
 
 	/* EC UART transmit is enabled.  Requires EC UART enabled. */
-	CCD_ENABLE_UART_EC_TX		= (1 << 3),
+	CCD_ENABLE_UART_EC_TX		= BIT(3),
 
 	/*
 	 * EC UART bit-banging is enabled.  Requires EC UART enabled, and
 	 * blocks EC UART transmit.
 	 */
-	CCD_ENABLE_UART_EC_BITBANG	= (1 << 4),
+	CCD_ENABLE_UART_EC_BITBANG	= BIT(4),
 
 	/* I2C port is enabled */
-	CCD_ENABLE_I2C			= (1 << 5),
+	CCD_ENABLE_I2C			= BIT(5),
 
 	/* SPI port is enabled for AP and/or EC flash */
-	CCD_ENABLE_SPI			= (1 << 6),
+	CCD_ENABLE_SPI			= BIT(6),
 };
 
 int console_is_restricted(void)
diff --git a/board/cr50/scratch_reg1.h b/board/cr50/scratch_reg1.h
index f4388ece18..6fdfe12181 100644
--- a/board/cr50/scratch_reg1.h
+++ b/board/cr50/scratch_reg1.h
@@ -11,8 +11,8 @@
  * Bit assignments of the LONG_LIFE_SCRATCH1 register. This register survives
  * all kinds of resets, it is cleared only on the Power ON event.
  */
-#define BOARD_SLAVE_CONFIG_SPI       (1 << 0)   /* TPM uses SPI interface */
-#define BOARD_SLAVE_CONFIG_I2C       (1 << 1)   /* TPM uses I2C interface */
+#define BOARD_SLAVE_CONFIG_SPI       BIT(0)   /* TPM uses SPI interface */
+#define BOARD_SLAVE_CONFIG_I2C       BIT(1)   /* TPM uses I2C interface */
 
 /*
  * The gaps are left to ensure backwards compatibility with the earliest cr50
@@ -21,20 +21,20 @@
  */
 
 /* TODO(crosbug.com/p/56945): Remove when sys_rst_l has an external pullup */
-#define BOARD_NEEDS_SYS_RST_PULL_UP  (1 << 5)   /* Add a pullup to sys_rst_l */
-#define BOARD_USE_PLT_RESET          (1 << 6)   /* Use plt_rst_l instead of */
+#define BOARD_NEEDS_SYS_RST_PULL_UP  BIT(5)   /* Add a pullup to sys_rst_l */
+#define BOARD_USE_PLT_RESET          BIT(6)   /* Use plt_rst_l instead of */
 						/* sys_rst_l to monitor the */
 						/* system resets */
 
 /* Bits to store write protect bit state across deep sleep and resets. */
-#define BOARD_WP_ASSERTED            (1 << 8)
-#define BOARD_FORCING_WP             (1 << 9)
+#define BOARD_WP_ASSERTED            BIT(8)
+#define BOARD_FORCING_WP             BIT(9)
 
 /*
  * Bit to signal to compatible RO to suppress its uart output.
  * Helps to reduce time to resume from deep sleep.
  */
-#define BOARD_NO_RO_UART             (1 << 10)
+#define BOARD_NO_RO_UART             BIT(10)
 
 /*
  * Bits to store current case-closed debug state across deep sleep.
@@ -46,18 +46,18 @@
 #define BOARD_CCD_STATE              (3 << BOARD_CCD_SHIFT)
 
 /* Prevent Cr50 from entering deep sleep when the AP is off */
-#define BOARD_DEEP_SLEEP_DISABLED    (1 << 13)
+#define BOARD_DEEP_SLEEP_DISABLED    BIT(13)
 /* Use Cr50_RX_AP_TX to determine if the AP is off or on */
-#define BOARD_DETECT_AP_WITH_UART    (1 << 14)
+#define BOARD_DETECT_AP_WITH_UART    BIT(14)
 
 /* ITE EC sync sequence generation after reset is required. */
-#define BOARD_ITE_EC_SYNC_NEEDED     (1 << 15)
+#define BOARD_ITE_EC_SYNC_NEEDED     BIT(15)
 
 /*
  * Enable delayed write protect disable for systems that can be opened
  * in less than 2 minutes
  */
-#define BOARD_WP_DISABLE_DELAY       (1 << 16)
+#define BOARD_WP_DISABLE_DELAY       BIT(16)
 /*
  * Enable custom options required for the closed source EC on the
  * Sarien/Arcada boards.  Includes the following behavior
@@ -67,18 +67,18 @@
  *    EC extended reset
  *    Power+Refresh recovery mode (instead of Power+Refresh+Esc)
  */
-#define BOARD_CLOSED_SOURCE_SET1     (1 << 17)
+#define BOARD_CLOSED_SOURCE_SET1     BIT(17)
 
 /*
  * Wait until PLT_RST_L is asserted before deasserting reset.
  */
-#define BOARD_CLOSED_LOOP_RESET      (1 << 18)
+#define BOARD_CLOSED_LOOP_RESET      BIT(18)
 
 /*
  * The board uses INA pins as GPIOs, so it can't support reading inas using usb
  * i2c.
  */
-#define BOARD_NO_INA_SUPPORT             (1 << 19)
+#define BOARD_NO_INA_SUPPORT             BIT(19)
 
 /*
  * Macro to capture all properties related to board strapping pins. This must be
diff --git a/board/cr50/wp.c b/board/cr50/wp.c
index 8c4980a70d..b1be6a87b5 100644
--- a/board/cr50/wp.c
+++ b/board/cr50/wp.c
@@ -277,7 +277,7 @@ int board_wipe_tpm(void)
  * git sha c7282f6.
  */
 #define FWMP_HASH_SIZE		    32
-#define FWMP_DEV_DISABLE_CCD_UNLOCK (1 << 6)
+#define FWMP_DEV_DISABLE_CCD_UNLOCK BIT(6)
 #define FIRMWARE_FLAG_DEV_MODE      0x02
 
 struct RollbackSpaceFirmware {
diff --git a/board/dingdong/board.c b/board/dingdong/board.c
index ae79cb5b6b..b03275555e 100644
--- a/board/dingdong/board.c
+++ b/board/dingdong/board.c
@@ -95,9 +95,9 @@ void hpd_event(enum gpio_signal signal)
 void board_config_pre_init(void)
 {
 	/* enable SYSCFG clock */
-	STM32_RCC_APB2ENR |= 1 << 0;
+	STM32_RCC_APB2ENR |= BIT(0);
 	/* Remap USART DMA to match the USART driver */
-	STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10);/* Remap USART1 RX/TX DMA */
+	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10);/* Remap USART1 RX/TX DMA */
 }
 
 /* Initialize board. */
diff --git a/board/dingdong/usb_pd_config.h b/board/dingdong/usb_pd_config.h
index 33e7225131..309c2200f9 100644
--- a/board/dingdong/usb_pd_config.h
+++ b/board/dingdong/usb_pd_config.h
@@ -50,7 +50,7 @@ static inline void spi_enable_clock(int port)
 #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
 #define TIM_CCR_CS  1
-#define EXTI_COMP_MASK(p) (1 << 21)
+#define EXTI_COMP_MASK(p) BIT(21)
 #define IRQ_COMP STM32_IRQ_COMP
 /* triggers packet detection on comparator falling edge */
 #define EXTI_XTSR STM32_EXTI_FTSR
@@ -71,8 +71,8 @@ static inline void pd_set_pins_speed(int port)
 static inline void pd_tx_spi_reset(int port)
 {
 	/* Reset SPI1 */
-	STM32_RCC_APB2RSTR |= (1 << 12);
-	STM32_RCC_APB2RSTR &= ~(1 << 12);
+	STM32_RCC_APB2RSTR |= BIT(12);
+	STM32_RCC_APB2RSTR &= ~BIT(12);
 }
 
 /* Drive the CC line from the TX block */
diff --git a/board/discovery-stm32f072/board.c b/board/discovery-stm32f072/board.c
index 7a16208498..2cc98da410 100644
--- a/board/discovery-stm32f072/board.c
+++ b/board/discovery-stm32f072/board.c
@@ -160,7 +160,7 @@ const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 void usb_spi_board_enable(struct usb_spi_config const *config)
 {
 	/* Remap SPI2 to DMA channels 6 and 7 */
-	STM32_SYSCFG_CFGR1 |= (1 << 24);
+	STM32_SYSCFG_CFGR1 |= BIT(24);
 
 	/* Configure SPI GPIOs */
 	gpio_config_module(MODULE_SPI_FLASH, 1);
diff --git a/board/eve/board.c b/board/eve/board.c
index 1af42167b3..ea213d9b9f 100644
--- a/board/eve/board.c
+++ b/board/eve/board.c
@@ -374,7 +374,7 @@ static void board_report_pmic_fault(const char *str)
 	    != EC_SUCCESS)
 		return;
 
-	if (!(vrfault & (1 << 4)))
+	if (!(vrfault & BIT(4)))
 		return;
 
 	/* VRFAULT has occurred, print VRFAULT status bits. */
@@ -390,7 +390,7 @@ static void board_report_pmic_fault(const char *str)
 		pwrstat2);
 
 	/* Clear all faults -- Write 1 to clear. */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, (1 << 4));
+	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, BIT(4));
 	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x16, pwrstat1);
 	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x17, pwrstat2);
 
@@ -901,7 +901,7 @@ struct motion_sensor_t motion_sensors[] = {
 	 .drv_data = &g_bmi160_data,
 	 .port = I2C_PORT_GYRO,
 	 .addr = BMI160_ADDR0,
-	 .default_range = 1 << 11, /* 16LSB / uT, fixed */
+	 .default_range = BIT(11), /* 16LSB / uT, fixed */
 	 .rot_standard_ref = &mag_standard_ref,
 	 .min_frequency = BMM150_MAG_MIN_FREQ,
 	 .max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL),
diff --git a/board/fizz/board.c b/board/fizz/board.c
index 75450fd725..e200c4722e 100644
--- a/board/fizz/board.c
+++ b/board/fizz/board.c
@@ -703,7 +703,7 @@ static const struct charge_port_info bj_adapters[] = {
  * KBL-U Celeron 3965	7	65
  * KBL-U Celeron 3865	0	65
  */
-#define BJ_ADAPTER_90W_MASK (1 << 4 | 1 << 5 | 1 << 6)
+#define BJ_ADAPTER_90W_MASK (BIT(4) | BIT(5) | BIT(6))
 
 static void setup_bj(void)
 {
diff --git a/board/flapjack/board.h b/board/flapjack/board.h
index 8ca624a1f2..3cf5bacc64 100644
--- a/board/flapjack/board.h
+++ b/board/flapjack/board.h
@@ -210,7 +210,7 @@
 		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC))
 
 /* Define panel size mask according to skuid */
-#define SKU_ID_PANEL_SIZE_MASK  (1 << 1)
+#define SKU_ID_PANEL_SIZE_MASK  BIT(1)
 
 #ifndef __ASSEMBLER__
 
diff --git a/board/glados_pd/board.c b/board/glados_pd/board.c
index f97845aa24..07ac9b7f06 100644
--- a/board/glados_pd/board.c
+++ b/board/glados_pd/board.c
@@ -37,7 +37,7 @@ void pd_send_ec_int(void)
 void board_config_pre_init(void)
 {
 	/* enable SYSCFG clock */
-	STM32_RCC_APB2ENR |= 1 << 0;
+	STM32_RCC_APB2ENR |= BIT(0);
 	/*
 	 * the DMA mapping is :
 	 *  Chan 2 : TIM1_CH1  (C0 RX)
diff --git a/board/glados_pd/usb_pd_config.h b/board/glados_pd/usb_pd_config.h
index 8df3f84dc1..4eee78383d 100644
--- a/board/glados_pd/usb_pd_config.h
+++ b/board/glados_pd/usb_pd_config.h
@@ -72,7 +72,7 @@ static inline void spi_enable_clock(int port)
  * EXTI line 22 is connected to the CMP2 output,
  * C0 uses CMP2, and C1 uses CMP1.
  */
-#define EXTI_COMP_MASK(p) ((p) ? (1<<21) : (1 << 22))
+#define EXTI_COMP_MASK(p) ((p) ? BIT(21) : BIT(22))
 
 #define IRQ_COMP STM32_IRQ_COMP
 /* triggers packet detection on comparator falling edge */
@@ -108,12 +108,12 @@ static inline void pd_tx_spi_reset(int port)
 {
 	if (port == 0) {
 		/* Reset SPI1 */
-		STM32_RCC_APB2RSTR |= (1 << 12);
-		STM32_RCC_APB2RSTR &= ~(1 << 12);
+		STM32_RCC_APB2RSTR |= BIT(12);
+		STM32_RCC_APB2RSTR &= ~BIT(12);
 	} else {
 		/* Reset SPI2 */
-		STM32_RCC_APB1RSTR |= (1 << 14);
-		STM32_RCC_APB1RSTR &= ~(1 << 14);
+		STM32_RCC_APB1RSTR |= BIT(14);
+		STM32_RCC_APB1RSTR &= ~BIT(14);
 	}
 }
 
diff --git a/board/glkrvp/chg_usb_pd.c b/board/glkrvp/chg_usb_pd.c
index 152e79142b..c10c1e14a4 100644
--- a/board/glkrvp/chg_usb_pd.c
+++ b/board/glkrvp/chg_usb_pd.c
@@ -19,10 +19,10 @@
 #define PTN5110_EXT_GPIO_CONFIG		0x92
 #define PTN5110_EXT_GPIO_CONTROL	0x93
 
-#define PTN5110_EXT_GPIO_FRS_EN			(1 << 6)
-#define PTN5110_EXT_GPIO_EN_SRC			(1 << 5)
-#define PTN5110_EXT_GPIO_EN_SNK1		(1 << 4)
-#define PTN5110_EXT_GPIO_IILIM_5V_VBUS_L	(1 << 3)
+#define PTN5110_EXT_GPIO_FRS_EN			BIT(6)
+#define PTN5110_EXT_GPIO_EN_SRC			BIT(5)
+#define PTN5110_EXT_GPIO_EN_SNK1		BIT(4)
+#define PTN5110_EXT_GPIO_IILIM_5V_VBUS_L	BIT(3)
 
 enum glkrvp_charge_ports {
 	TYPE_C_PORT_0,
diff --git a/board/glkrvp_ite/chg_usb_pd.c b/board/glkrvp_ite/chg_usb_pd.c
index 0b1a188081..1ddef2c60d 100644
--- a/board/glkrvp_ite/chg_usb_pd.c
+++ b/board/glkrvp_ite/chg_usb_pd.c
@@ -19,10 +19,10 @@
 #define PTN5110_EXT_GPIO_CONFIG		0x92
 #define PTN5110_EXT_GPIO_CONTROL	0x93
 
-#define PTN5110_EXT_GPIO_FRS_EN			(1 << 6)
-#define PTN5110_EXT_GPIO_EN_SRC			(1 << 5)
-#define PTN5110_EXT_GPIO_EN_SNK1		(1 << 4)
-#define PTN5110_EXT_GPIO_IILIM_5V_VBUS_L	(1 << 3)
+#define PTN5110_EXT_GPIO_FRS_EN			BIT(6)
+#define PTN5110_EXT_GPIO_EN_SRC			BIT(5)
+#define PTN5110_EXT_GPIO_EN_SNK1		BIT(4)
+#define PTN5110_EXT_GPIO_IILIM_5V_VBUS_L	BIT(3)
 
 enum glkrvp_charge_ports {
 	TYPE_C_PORT_0,
diff --git a/board/hammer/board.c b/board/hammer/board.c
index 06f231e25a..8b3de4268c 100644
--- a/board/hammer/board.c
+++ b/board/hammer/board.c
@@ -224,7 +224,7 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_INIT_PWM - 1);
 void board_config_pre_init(void)
 {
 	/* enable SYSCFG clock */
-	STM32_RCC_APB2ENR |= 1 << 0;
+	STM32_RCC_APB2ENR |= BIT(0);
 
 	/* Remap USART DMA to match the USART driver */
 	/*
@@ -232,7 +232,7 @@ void board_config_pre_init(void)
 	 *  Chan 4 : USART1_TX
 	 *  Chan 5 : USART1_RX
 	 */
-	STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10); /* Remap USART1 RX/TX DMA */
+	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10); /* Remap USART1 RX/TX DMA */
 }
 
 int board_has_keyboard_backlight(void)
diff --git a/board/hoho/board.c b/board/hoho/board.c
index e6258f19b4..69ef58f59c 100644
--- a/board/hoho/board.c
+++ b/board/hoho/board.c
@@ -97,9 +97,9 @@ void hpd_event(enum gpio_signal signal)
 void board_config_pre_init(void)
 {
 	/* enable SYSCFG clock */
-	STM32_RCC_APB2ENR |= 1 << 0;
+	STM32_RCC_APB2ENR |= BIT(0);
 	/* Remap USART DMA to match the USART driver */
-	STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10);/* Remap USART1 RX/TX DMA */
+	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10);/* Remap USART1 RX/TX DMA */
 }
 
 #ifdef CONFIG_SPI_FLASH
@@ -107,7 +107,7 @@ void board_config_pre_init(void)
 static void board_init_spi2(void)
 {
 	/* Remap SPI2 to DMA channels 6 and 7 */
-	STM32_SYSCFG_CFGR1 |= (1 << 24);
+	STM32_SYSCFG_CFGR1 |= BIT(24);
 
 	/* Set pin NSS to general purpose output mode (01b). */
 	/* Set pins SCK, MISO, and MOSI to alternate function (10b). */
@@ -127,8 +127,8 @@ static void board_init_spi2(void)
 	STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
 
 	/* Reset SPI2 */
-	STM32_RCC_APB1RSTR |= (1 << 14);
-	STM32_RCC_APB1RSTR &= ~(1 << 14);
+	STM32_RCC_APB1RSTR |= BIT(14);
+	STM32_RCC_APB1RSTR &= ~BIT(14);
 
 	/* Enable clocks to SPI2 module */
 	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
diff --git a/board/hoho/usb_pd_config.h b/board/hoho/usb_pd_config.h
index 33e7225131..309c2200f9 100644
--- a/board/hoho/usb_pd_config.h
+++ b/board/hoho/usb_pd_config.h
@@ -50,7 +50,7 @@ static inline void spi_enable_clock(int port)
 #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
 #define TIM_CCR_CS  1
-#define EXTI_COMP_MASK(p) (1 << 21)
+#define EXTI_COMP_MASK(p) BIT(21)
 #define IRQ_COMP STM32_IRQ_COMP
 /* triggers packet detection on comparator falling edge */
 #define EXTI_XTSR STM32_EXTI_FTSR
@@ -71,8 +71,8 @@ static inline void pd_set_pins_speed(int port)
 static inline void pd_tx_spi_reset(int port)
 {
 	/* Reset SPI1 */
-	STM32_RCC_APB2RSTR |= (1 << 12);
-	STM32_RCC_APB2RSTR &= ~(1 << 12);
+	STM32_RCC_APB2RSTR |= BIT(12);
+	STM32_RCC_APB2RSTR &= ~BIT(12);
 }
 
 /* Drive the CC line from the TX block */
diff --git a/board/host/charger.c b/board/host/charger.c
index 0ec8ab605c..29774359ef 100644
--- a/board/host/charger.c
+++ b/board/host/charger.c
@@ -24,7 +24,7 @@ static const struct charger_info mock_charger_info = {
 	.input_current_step = 128,
 };
 
-#define OPTION_CHARGE_INHIBIT (1 << 0)
+#define OPTION_CHARGE_INHIBIT BIT(0)
 
 static uint32_t mock_option;
 static uint32_t mock_mode;
diff --git a/board/jerry/board.c b/board/jerry/board.c
index 5c7eb8c41f..cbc3d21c16 100644
--- a/board/jerry/board.c
+++ b/board/jerry/board.c
@@ -48,7 +48,7 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 void board_config_pre_init(void)
 {
 	/* enable SYSCFG clock */
-	STM32_RCC_APB2ENR |= 1 << 0;
+	STM32_RCC_APB2ENR |= BIT(0);
 
 	/* Remap USART DMA to match the USART driver */
 	/*
@@ -58,5 +58,5 @@ void board_config_pre_init(void)
 	 *  Chan 4 : USART1_TX
 	 *  Chan 5 : USART1_RX
 	 */
-	STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10); /* Remap USART1 RX/TX DMA */
+	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10); /* Remap USART1 RX/TX DMA */
 }
diff --git a/board/kukui/board.c b/board/kukui/board.c
index f0a32d1583..1c36b5d119 100644
--- a/board/kukui/board.c
+++ b/board/kukui/board.c
@@ -426,7 +426,7 @@ struct motion_sensor_t motion_sensors[] = {
 	 .drv_data = &g_bmi160_data,
 	 .port = I2C_PORT_ACCEL,
 	 .addr = BMI160_ADDR0,
-	 .default_range = 1 << 11, /* 16LSB / uT, fixed */
+	 .default_range = BIT(11), /* 16LSB / uT, fixed */
 	 .rot_standard_ref = &mag_standard_ref,
 	 .min_frequency = BMM150_MAG_MIN_FREQ,
 	 .max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL),
diff --git a/board/mchpevb1/board.c b/board/mchpevb1/board.c
index eeeb557b96..79226d7d71 100644
--- a/board/mchpevb1/board.c
+++ b/board/mchpevb1/board.c
@@ -880,10 +880,10 @@ static void ds1624_update(void)
 			DS1624_READ_TEMP16, &temp);
 
 	d = (temp & 0x7FFF) >> 8;
-	if ((uint32_t)temp & (1 << 7))
+	if ((uint32_t)temp & BIT(7))
 		d++;
 
-	if ((uint32_t)temp & (1 << 15))
+	if ((uint32_t)temp & BIT(15))
 		d |= (1u << 31);
 
 	ds1624_temp = (int32_t)d;
diff --git a/board/nami/board.h b/board/nami/board.h
index 157ea5554b..45e58d49bc 100644
--- a/board/nami/board.h
+++ b/board/nami/board.h
@@ -301,9 +301,9 @@ enum model_id {
 	MODEL_BARD = 2,
 };
 
-#define SKU_ID_MASK_CONVERTIBLE	(1 << 9)
-#define SKU_ID_MASK_KEYPAD	(1 << 15)
-#define SKU_ID_MASK_UK2		(1 << 18)
+#define SKU_ID_MASK_CONVERTIBLE	BIT(9)
+#define SKU_ID_MASK_KEYPAD	BIT(15)
+#define SKU_ID_MASK_UK2		BIT(18)
 
 /* TODO(crosbug.com/p/61098): Verify the numbers below. */
 /*
diff --git a/board/nami/led.c b/board/nami/led.c
index a2866769c2..7f97d360e5 100644
--- a/board/nami/led.c
+++ b/board/nami/led.c
@@ -80,9 +80,9 @@ struct led_pattern {
 };
 
 #define PULSE_NO		0
-#define PULSE(interval)		(1 << 7 | (interval))
+#define PULSE(interval)		(BIT(7) | (interval))
 #define BLINK(interval) 	(interval)
-#define ALTERNATE(interval)	(1 << 6 | (interval))
+#define ALTERNATE(interval)	(BIT(6) | (interval))
 #define IS_PULSING(pulse)	((pulse) & 0x80)
 #define IS_ALTERNATE(pulse)	((pulse) & 0x40)
 #define PULSE_INTERVAL(pulse)	(((pulse) & 0x3f) * 100 * MSEC)
diff --git a/board/nautilus/board.c b/board/nautilus/board.c
index 71f979401d..b87ff0ed37 100644
--- a/board/nautilus/board.c
+++ b/board/nautilus/board.c
@@ -288,7 +288,7 @@ static void board_report_pmic_fault(const char *str)
 	    != EC_SUCCESS)
 		return;
 
-	if (!(vrfault & (1 << 4)))
+	if (!(vrfault & BIT(4)))
 		return;
 
 	/* VRFAULT has occurred, print VRFAULT status bits. */
@@ -304,7 +304,7 @@ static void board_report_pmic_fault(const char *str)
 		pwrstat2);
 
 	/* Clear all faults -- Write 1 to clear. */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, (1 << 4));
+	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, BIT(4));
 	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x16, pwrstat1);
 	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x17, pwrstat2);
 
diff --git a/board/nocturne/board.c b/board/nocturne/board.c
index c2a13f7655..c3ac854a26 100644
--- a/board/nocturne/board.c
+++ b/board/nocturne/board.c
@@ -544,7 +544,7 @@ static void board_pmic_init(void)
 	/* Mask V5A_DS3_PG from PMIC PGMASK1. */
 	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x18, &pgmask1))
 		return;
-	pgmask1 |= (1 << 2);
+	pgmask1 |= BIT(2);
 	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x18, pgmask1);
 
 	board_pmic_disable_slp_s0_vr_decay();
@@ -645,7 +645,7 @@ static void board_report_pmic_fault(const char *str)
 	    != EC_SUCCESS)
 		return;
 
-	if (!(vrfault & (1 << 4)))
+	if (!(vrfault & BIT(4)))
 		return;
 
 	/* VRFAULT has occurred, print VRFAULT status bits. */
@@ -661,7 +661,7 @@ static void board_report_pmic_fault(const char *str)
 		pwrstat2);
 
 	/* Clear all faults -- Write 1 to clear. */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, (1 << 4));
+	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, BIT(4));
 	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x16, pwrstat1);
 	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x17, pwrstat2);
 
@@ -799,7 +799,7 @@ uint16_t tcpc_get_alert_status(void)
 	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL)) {
 		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
 			/* The TCPCI spec says to ignore bits 14:12. */
-			regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+			regval &= ~(BIT(14) | BIT(13) | BIT(12));
 
 			if (regval)
 				status |= PD_STATUS_TCPC_ALERT_0;
@@ -809,7 +809,7 @@ uint16_t tcpc_get_alert_status(void)
 	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL)) {
 		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
 			/* TCPCI spec says to ignore bits 14:12. */
-			regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+			regval &= ~(BIT(14) | BIT(13) | BIT(12));
 
 			if (regval)
 				status |= PD_STATUS_TCPC_ALERT_1;
diff --git a/board/plankton/usb_pd_config.h b/board/plankton/usb_pd_config.h
index 74855344e2..4ef1d3707d 100644
--- a/board/plankton/usb_pd_config.h
+++ b/board/plankton/usb_pd_config.h
@@ -51,7 +51,7 @@ static inline void spi_enable_clock(int port)
 #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
 #define TIM_CCR_CS  1
-#define EXTI_COMP_MASK(p) (1 << 21)
+#define EXTI_COMP_MASK(p) BIT(21)
 #define IRQ_COMP STM32_IRQ_COMP
 /* triggers packet detection on comparator falling edge */
 #define EXTI_XTSR STM32_EXTI_FTSR
@@ -71,8 +71,8 @@ static inline void pd_set_pins_speed(int port)
 static inline void pd_tx_spi_reset(int port)
 {
 	/* Reset SPI1 */
-	STM32_RCC_APB2RSTR |= (1 << 12);
-	STM32_RCC_APB2RSTR &= ~(1 << 12);
+	STM32_RCC_APB2RSTR |= BIT(12);
+	STM32_RCC_APB2RSTR &= ~BIT(12);
 }
 
 /* Drive the CC line from the TX block */
diff --git a/board/poppy/board.c b/board/poppy/board.c
index 3a158ef050..235389fc89 100644
--- a/board/poppy/board.c
+++ b/board/poppy/board.c
@@ -378,7 +378,7 @@ static void board_report_pmic_fault(const char *str)
 	    != EC_SUCCESS)
 		return;
 
-	if (!(vrfault & (1 << 4)))
+	if (!(vrfault & BIT(4)))
 		return;
 
 	/* VRFAULT has occurred, print VRFAULT status bits. */
@@ -394,7 +394,7 @@ static void board_report_pmic_fault(const char *str)
 		pwrstat2);
 
 	/* Clear all faults -- Write 1 to clear. */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, (1 << 4));
+	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, BIT(4));
 	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x16, pwrstat1);
 	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x17, pwrstat2);
 
@@ -808,7 +808,7 @@ struct motion_sensor_t motion_sensors[] = {
 	 .drv_data = &g_bmi160_data,
 	 .port = I2C_PORT_GYRO,
 	 .addr = BMI160_ADDR0,
-	 .default_range = 1 << 11, /* 16LSB / uT, fixed */
+	 .default_range = BIT(11), /* 16LSB / uT, fixed */
 	 .rot_standard_ref = &mag_standard_ref,
 	 .min_frequency = BMM150_MAG_MIN_FREQ,
 	 .max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL),
diff --git a/board/rainier/board.c b/board/rainier/board.c
index a8211560d7..1065bbf6ef 100644
--- a/board/rainier/board.c
+++ b/board/rainier/board.c
@@ -416,7 +416,7 @@ struct motion_sensor_t motion_sensors[] = {
 	 .drv_data = &bmp280_drv_data,
 	 .port = CONFIG_SPI_ACCEL_PORT,
 	 .addr = BMI160_SET_SPI_ADDRESS(CONFIG_SPI_ACCEL_PORT),
-	 .default_range = 1 << 18, /*  1bit = 4 Pa, 16bit ~= 2600 hPa */
+	 .default_range = BIT(18), /*  1bit = 4 Pa, 16bit ~= 2600 hPa */
 	 .min_frequency = BMP280_BARO_MIN_FREQ,
 	 .max_frequency = BMP280_BARO_MAX_FREQ,
 	},
diff --git a/board/rammus/board.c b/board/rammus/board.c
index d4ec8ea13a..7497ac8aa5 100644
--- a/board/rammus/board.c
+++ b/board/rammus/board.c
@@ -312,7 +312,7 @@ static void board_report_pmic_fault(const char *str)
 	    != EC_SUCCESS)
 		return;
 
-	if (!(vrfault & (1 << 4)))
+	if (!(vrfault & BIT(4)))
 		return;
 
 	/* VRFAULT has occurred, print VRFAULT status bits. */
@@ -328,7 +328,7 @@ static void board_report_pmic_fault(const char *str)
 		pwrstat2);
 
 	/* Clear all faults -- Write 1 to clear. */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, (1 << 4));
+	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, BIT(4));
 	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x16, pwrstat1);
 	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x17, pwrstat2);
 
diff --git a/board/reef/board.c b/board/reef/board.c
index beeb5d823f..2579b103fc 100644
--- a/board/reef/board.c
+++ b/board/reef/board.c
@@ -803,7 +803,7 @@ struct motion_sensor_t motion_sensors[] = {
 	 .drv_data = &g_bmi160_data,
 	 .port = I2C_PORT_GYRO,
 	 .addr = BMI160_ADDR0,
-	 .default_range = 1 << 11, /* 16LSB / uT, fixed */
+	 .default_range = BIT(11), /* 16LSB / uT, fixed */
 	 .rot_standard_ref = &mag_standard_ref,
 	 .min_frequency = BMM150_MAG_MIN_FREQ,
 	 .max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL),
@@ -818,7 +818,7 @@ struct motion_sensor_t motion_sensors[] = {
 	 .drv_data = &bmp280_drv_data,
 	 .port = I2C_PORT_BARO,
 	 .addr = BMP280_I2C_ADDRESS1,
-	 .default_range = 1 << 18, /*  1bit = 4 Pa, 16bit ~= 2600 hPa */
+	 .default_range = BIT(18), /*  1bit = 4 Pa, 16bit ~= 2600 hPa */
 	 .min_frequency = BMP280_BARO_MIN_FREQ,
 	 .max_frequency = BMP280_BARO_MAX_FREQ,
 	},
diff --git a/board/reef_mchp/board.c b/board/reef_mchp/board.c
index ecf938d179..7547b82167 100644
--- a/board/reef_mchp/board.c
+++ b/board/reef_mchp/board.c
@@ -1052,7 +1052,7 @@ struct motion_sensor_t motion_sensors[] = {
 	 .drv_data = &g_bmi160_data,
 	 .port = I2C_PORT_GYRO,
 	 .addr = BMI160_ADDR0,
-	 .default_range = 1 << 11, /* 16LSB / uT, fixed */
+	 .default_range = BIT(11), /* 16LSB / uT, fixed */
 	 .rot_standard_ref = &mag_standard_ref,
 	 .min_frequency = BMM150_MAG_MIN_FREQ,
 	 .max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL),
@@ -1067,7 +1067,7 @@ struct motion_sensor_t motion_sensors[] = {
 	 .drv_data = &bmp280_drv_data,
 	 .port = I2C_PORT_BARO,
 	 .addr = BMP280_I2C_ADDRESS1,
-	 .default_range = 1 << 18, /*  1bit = 4 Pa, 16bit ~= 2600 hPa */
+	 .default_range = BIT(18), /*  1bit = 4 Pa, 16bit ~= 2600 hPa */
 	 .min_frequency = BMP280_BARO_MIN_FREQ,
 	 .max_frequency = BMP280_BARO_MAX_FREQ,
 	},
diff --git a/board/samus/board.c b/board/samus/board.c
index b8f66ca101..9f5bcf743a 100644
--- a/board/samus/board.c
+++ b/board/samus/board.c
@@ -87,7 +87,7 @@ const struct adc_t adc_channels[] = {
 	 * now.
 	 */
 	{"BatteryTemp", LM4_ADC_SEQ2, 1, 1, 0,
-	 LM4_AIN(10), 0x06 /* IE0 | END0 */, LM4_GPIO_B, (1<<4)},
+	 LM4_AIN(10), 0x06 /* IE0 | END0 */, LM4_GPIO_B, BIT(4)},
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
diff --git a/board/samus/board.h b/board/samus/board.h
index 59c3e8ca4d..ac76ff0d4c 100644
--- a/board/samus/board.h
+++ b/board/samus/board.h
@@ -202,8 +202,8 @@ void bkboost_det_interrupt(enum gpio_signal signal);
 void jtag_interrupt(enum gpio_signal signal);
 
 /* Bit masks for turning on PP5000 rail in G3 */
-#define PP5000_IN_G3_AC       (1 << 0)
-#define PP5000_IN_G3_LIGHTBAR (1 << 1)
+#define PP5000_IN_G3_AC       BIT(0)
+#define PP5000_IN_G3_LIGHTBAR BIT(1)
 
 /* Enable/disable PP5000 rail mask in G3 */
 void set_pp5000_in_g3(int mask, int enable);
diff --git a/board/samus/panel.c b/board/samus/panel.c
index 970197b9c8..961cb6fafe 100644
--- a/board/samus/panel.c
+++ b/board/samus/panel.c
@@ -35,7 +35,7 @@
 #define  LP8555_REG_CURRENT_MAXCURR_50MA  0x07
 #define LP8555_REG_STEP           0x15
 #define  LP8555_REG_STEP_STEP_0MS           (0 << 0)
-#define  LP8555_REG_STEP_STEP_8MS           (1 << 0)
+#define  LP8555_REG_STEP_STEP_8MS           BIT(0)
 #define  LP8555_REG_STEP_STEP_16MS          (2 << 0)
 #define  LP8555_REG_STEP_STEP_24MS          (3 << 0)
 #define  LP8555_REG_STEP_STEP_28MS          (4 << 0)
@@ -43,7 +43,7 @@
 #define  LP8555_REG_STEP_STEP_100MS         (6 << 0)
 #define  LP8555_REG_STEP_STEP_200MS         (7 << 0)
 #define  LP8555_REG_STEP_PWM_IN_HYST_NONE   (0 << 3)
-#define  LP8555_REG_STEP_PWM_IN_HYST_1LSB   (1 << 3)
+#define  LP8555_REG_STEP_PWM_IN_HYST_1LSB   BIT(3)
 #define  LP8555_REG_STEP_PWM_IN_HYST_2LSB   (2 << 3)
 #define  LP8555_REG_STEP_PWM_IN_HYST_4LSB   (3 << 3)
 #define  LP8555_REG_STEP_PWM_IN_HYST_8LSB   (4 << 3)
@@ -51,7 +51,7 @@
 #define  LP8555_REG_STEP_PWM_IN_HYST_32LSB  (6 << 3)
 #define  LP8555_REG_STEP_PWM_IN_HYST_64LSB  (7 << 3)
 #define  LP8555_REG_STEP_SMOOTH_NONE        (0 << 6)
-#define  LP8555_REG_STEP_SMOOTH_LIGHT       (1 << 6)
+#define  LP8555_REG_STEP_SMOOTH_LIGHT       BIT(6)
 #define  LP8555_REG_STEP_SMOOTH_MEDIUM      (2 << 6)
 #define  LP8555_REG_STEP_SMOOTH_HEAVY       (3 << 6)
 
diff --git a/board/samus_pd/board.c b/board/samus_pd/board.c
index 3087b9ce03..7691865476 100644
--- a/board/samus_pd/board.c
+++ b/board/samus_pd/board.c
@@ -181,7 +181,7 @@ void pch_evt(enum gpio_signal signal)
 void board_config_pre_init(void)
 {
 	/* enable SYSCFG clock */
-	STM32_RCC_APB2ENR |= 1 << 0;
+	STM32_RCC_APB2ENR |= BIT(0);
 	/*
 	 * the DMA mapping is :
 	 *  Chan 2 : TIM1_CH1  (C0 RX)
@@ -196,7 +196,7 @@ void board_config_pre_init(void)
 	 * Remap USART1 RX/TX DMA to match uart driver. Remap SPI2 RX/TX and
 	 * TIM3_CH1 for unique DMA channels.
 	 */
-	STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10) | (1 << 24) | (1 << 30);
+	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10) | BIT(24) | BIT(30);
 }
 
 #include "gpio_list.h"
diff --git a/board/samus_pd/usb_pd_config.h b/board/samus_pd/usb_pd_config.h
index d303ae3a51..0f152a7362 100644
--- a/board/samus_pd/usb_pd_config.h
+++ b/board/samus_pd/usb_pd_config.h
@@ -64,7 +64,7 @@ static inline void spi_enable_clock(int port)
 #define TIM_TX_CCR_IDX(p) ((p) ? TIM_TX_CCR_C1 : TIM_TX_CCR_C0)
 #define TIM_RX_CCR_IDX(p) ((p) ? TIM_RX_CCR_C1 : TIM_RX_CCR_C0)
 #define TIM_CCR_CS  1
-#define EXTI_COMP_MASK(p) ((p) ? (1<<22) : (1 << 21))
+#define EXTI_COMP_MASK(p) ((p) ? BIT(22) : BIT(21))
 #define IRQ_COMP STM32_IRQ_COMP
 /* triggers packet detection on comparator falling edge */
 #define EXTI_XTSR STM32_EXTI_FTSR
@@ -93,12 +93,12 @@ static inline void pd_tx_spi_reset(int port)
 {
 	if (port == 0) {
 		/* Reset SPI2 */
-		STM32_RCC_APB1RSTR |= (1 << 14);
-		STM32_RCC_APB1RSTR &= ~(1 << 14);
+		STM32_RCC_APB1RSTR |= BIT(14);
+		STM32_RCC_APB1RSTR &= ~BIT(14);
 	} else {
 		/* Reset SPI1 */
-		STM32_RCC_APB2RSTR |= (1 << 12);
-		STM32_RCC_APB2RSTR &= ~(1 << 12);
+		STM32_RCC_APB2RSTR |= BIT(12);
+		STM32_RCC_APB2RSTR &= ~BIT(12);
 	}
 }
 
diff --git a/board/servo_micro/board.c b/board/servo_micro/board.c
index db6d8b197a..e717d6207b 100644
--- a/board/servo_micro/board.c
+++ b/board/servo_micro/board.c
@@ -43,12 +43,12 @@ void board_config_pre_init(void)
 	 *  i2c : no dma
 	 *  tim16/17: no dma
 	 */
-	STM32_SYSCFG_CFGR1 |= (1 << 26);  /* Remap USART3 RX/TX DMA */
+	STM32_SYSCFG_CFGR1 |= BIT(26);  /* Remap USART3 RX/TX DMA */
 
 	/* Remap SPI2 to DMA channels 6 and 7 */
 	/* STM32F072 SPI2 defaults to using DMA channels 4 and 5 */
 	/* but cros_ec hardcodes a 6/7 assumption in registers.h */
-	STM32_SYSCFG_CFGR1 |= (1 << 24);
+	STM32_SYSCFG_CFGR1 |= BIT(24);
 
 }
 
diff --git a/board/servo_v4/board.c b/board/servo_v4/board.c
index 982ed9ccfb..6890027346 100644
--- a/board/servo_v4/board.c
+++ b/board/servo_v4/board.c
@@ -41,7 +41,7 @@
 void board_config_pre_init(void)
 {
 	/* enable SYSCFG clock */
-	STM32_RCC_APB2ENR |= 1 << 0;
+	STM32_RCC_APB2ENR |= BIT(0);
 
 	/*
 	 * the DMA mapping is :
@@ -60,13 +60,13 @@ void board_config_pre_init(void)
 	 * Reference Manual
 	 */
 	/* Remap USART1 Tx from DMA channel 2 to channel 4 */
-	STM32_SYSCFG_CFGR1 |= (1 << 9);
+	STM32_SYSCFG_CFGR1 |= BIT(9);
 	/* Remap USART1 Rx from DMA channel 3 to channel 5 */
-	STM32_SYSCFG_CFGR1 |= (1 << 10);
+	STM32_SYSCFG_CFGR1 |= BIT(10);
 	/* Remap TIM3_CH1 from DMA channel 4 to channel 6 */
-	STM32_SYSCFG_CFGR1 |= (1 << 30);
+	STM32_SYSCFG_CFGR1 |= BIT(30);
 	/* Remap SPI2 Tx from DMA channel 5 to channel 7 */
-	STM32_SYSCFG_CFGR1 |= (1 << 24);
+	STM32_SYSCFG_CFGR1 |= BIT(24);
 }
 
 /******************************************************************************
diff --git a/board/servo_v4/usb_pd_config.h b/board/servo_v4/usb_pd_config.h
index 56c8d3aa02..41963a8360 100644
--- a/board/servo_v4/usb_pd_config.h
+++ b/board/servo_v4/usb_pd_config.h
@@ -83,7 +83,7 @@ static inline void spi_enable_clock(int port)
  * EXTI line 22 is connected to the CMP2 output,
  * CHG uses CMP2, and DUT uses CMP1.
  */
-#define EXTI_COMP_MASK(p) ((p) ? (1<<21) : (1 << 22))
+#define EXTI_COMP_MASK(p) ((p) ? (1<<21) : BIT(22))
 
 #define IRQ_COMP STM32_IRQ_COMP
 /* triggers packet detection on comparator falling edge */
@@ -119,12 +119,12 @@ static inline void pd_tx_spi_reset(int port)
 {
 	if (port == 0) {
 		/* Reset SPI1 */
-		STM32_RCC_APB2RSTR |= (1 << 12);
-		STM32_RCC_APB2RSTR &= ~(1 << 12);
+		STM32_RCC_APB2RSTR |= BIT(12);
+		STM32_RCC_APB2RSTR &= ~BIT(12);
 	} else {
 		/* Reset SPI2 */
-		STM32_RCC_APB1RSTR |= (1 << 14);
-		STM32_RCC_APB1RSTR &= ~(1 << 14);
+		STM32_RCC_APB1RSTR |= BIT(14);
+		STM32_RCC_APB1RSTR &= ~BIT(14);
 	}
 }
 
diff --git a/board/twinkie/board.c b/board/twinkie/board.c
index 513d45d9a7..f15a55400c 100644
--- a/board/twinkie/board.c
+++ b/board/twinkie/board.c
@@ -34,10 +34,10 @@ void vbus_event(enum gpio_signal signal)
 void board_config_pre_init(void)
 {
 	/* enable SYSCFG clock */
-	STM32_RCC_APB2ENR |= 1 << 0;
+	STM32_RCC_APB2ENR |= BIT(0);
 	/* Remap USART DMA to match the USART driver and TIM2 DMA */
-	STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10) /* Remap USART1 RX/TX DMA */
-			   |  (1 << 29);/* Remap TIM2 DMA */
+	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10) /* Remap USART1 RX/TX DMA */
+			   |  BIT(29);/* Remap TIM2 DMA */
 	/* 40 MHz pin speed on UART PA9/PA10 */
 	STM32_GPIO_OSPEEDR(GPIO_A) |= 0x003C0000;
 	/* 40 MHz pin speed on TX clock out PB9 */
diff --git a/board/twinkie/simpletrace.c b/board/twinkie/simpletrace.c
index e2ee05daab..dc116d951a 100644
--- a/board/twinkie/simpletrace.c
+++ b/board/twinkie/simpletrace.c
@@ -223,7 +223,7 @@ void trace_packets(void)
 	dma_disable(STM32_DMAC_CH7);
 	task_disable_irq(STM32_IRQ_DMA_CHANNEL_4_7);
 	/* remove TIM1 CH1/2/3 DMA remapping */
-	STM32_SYSCFG_CFGR1 &= ~(1 << 28);
+	STM32_SYSCFG_CFGR1 &= ~BIT(28);
 #endif
 
 	/* "classical" PD RX configuration */
diff --git a/board/twinkie/sniffer.c b/board/twinkie/sniffer.c
index dbdcbb68a7..e35b457ff7 100644
--- a/board/twinkie/sniffer.c
+++ b/board/twinkie/sniffer.c
@@ -256,7 +256,7 @@ static void rx_timer_init(int tim_id, timer_ctlr_t *tim, int ch_idx, int up_idx)
 void sniffer_init(void)
 {
 	/* remap TIM1 CH1/2/3 to DMA channel 6 */
-	STM32_SYSCFG_CFGR1 |= 1 << 28;
+	STM32_SYSCFG_CFGR1 |= BIT(28);
 
 	/* TIM1 CH1 for CC1 RX */
 	rx_timer_init(TIM_RX1, (void *)STM32_TIM_BASE(TIM_RX1),
@@ -266,7 +266,7 @@ void sniffer_init(void)
 		      TIM_RX2_CCR_IDX, 2);
 
 	/* turn on COMP/SYSCFG */
-	STM32_RCC_APB2ENR |= 1 << 0;
+	STM32_RCC_APB2ENR |= BIT(0);
 	STM32_COMP_CSR = STM32_COMP_CMP1EN | STM32_COMP_CMP1MODE_HSPEED |
 			 STM32_COMP_CMP1INSEL_VREF12 |
 			 STM32_COMP_CMP1OUTSEL_TIM1_IC1 |
diff --git a/board/twinkie/usb_pd_config.h b/board/twinkie/usb_pd_config.h
index b125a2dfa9..1b2c22ba1a 100644
--- a/board/twinkie/usb_pd_config.h
+++ b/board/twinkie/usb_pd_config.h
@@ -51,7 +51,7 @@ static inline void spi_enable_clock(int port)
 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
 #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
 #define TIM_CCR_CS  1
-#define EXTI_COMP_MASK(p) ((1 << 21) | (1 << 22))
+#define EXTI_COMP_MASK(p) (BIT(21) | BIT(22))
 #define IRQ_COMP STM32_IRQ_COMP
 /* triggers packet detection on comparator falling edge */
 #define EXTI_XTSR STM32_EXTI_FTSR
@@ -71,8 +71,8 @@ static inline void pd_set_pins_speed(int port)
 static inline void pd_tx_spi_reset(int port)
 {
 	/* Reset SPI1 */
-	STM32_RCC_APB2RSTR |= (1 << 12);
-	STM32_RCC_APB2RSTR &= ~(1 << 12);
+	STM32_RCC_APB2RSTR |= BIT(12);
+	STM32_RCC_APB2RSTR &= ~BIT(12);
 }
 
 /* Drive the CC line from the TX block */
diff --git a/board/zinger/hardware.c b/board/zinger/hardware.c
index c3cf2b5f4a..1d2ffb1eb3 100644
--- a/board/zinger/hardware.c
+++ b/board/zinger/hardware.c
@@ -17,12 +17,12 @@
 static void system_init(void)
 {
 	/* Enable access to RCC CSR register and RTC backup registers */
-	STM32_PWR_CR |= 1 << 8;
+	STM32_PWR_CR |= BIT(8);
 
 	/* switch on LSI */
-	STM32_RCC_CSR |= 1 << 0;
+	STM32_RCC_CSR |= BIT(0);
 	/* Wait for LSI to be ready */
-	while (!(STM32_RCC_CSR & (1 << 1)))
+	while (!(STM32_RCC_CSR & BIT(1)))
 		;
 	/* re-configure RTC if needed */
 	if ((STM32_RCC_BDCR & 0x00018300) != 0x00008200) {
@@ -108,7 +108,7 @@ static void adc_init(void)
 			;
 	}
 	/* Single conversion, right aligned, 12-bit */
-	STM32_ADC_CFGR1 = 1 << 12; /* (1 << 15) => AUTOOFF */;
+	STM32_ADC_CFGR1 = BIT(12); /* BIT(15) => AUTOOFF */;
 	/* clock is ADCCLK (ADEN must be off when writing this reg) */
 	STM32_ADC_CFGR2 = 0;
 	/* Sampling time : 71.5 ADC clock cycles, about 5us */
@@ -172,9 +172,9 @@ void hardware_init(void)
 	power_init();
 
 	/* Clear the hardware reset cause by setting the RMVF bit */
-	STM32_RCC_CSR |= 1 << 24;
+	STM32_RCC_CSR |= BIT(24);
 	/* Clear SBF in PWR_CSR */
-	STM32_PWR_CR |= 1 << 3;
+	STM32_PWR_CR |= BIT(3);
 
 	/*
 	 * WORKAROUND: as we cannot de-activate the watchdog during
@@ -206,7 +206,7 @@ static int adc_enable_last_watchdog(void)
 
 static inline int adc_watchdog_enabled(void)
 {
-	return STM32_ADC_CFGR1 & (1 << 23);
+	return STM32_ADC_CFGR1 & BIT(23);
 }
 
 int adc_read_channel(enum adc_channel ch)
@@ -222,9 +222,9 @@ int adc_read_channel(enum adc_channel ch)
 	/* Clear flags */
 	STM32_ADC_ISR = 0x8e;
 	/* Start conversion */
-	STM32_ADC_CR |= 1 << 2; /* ADSTART */
+	STM32_ADC_CR |= BIT(2); /* ADSTART */
 	/* Wait for end of conversion */
-	while (!(STM32_ADC_ISR & (1 << 2)))
+	while (!(STM32_ADC_ISR & BIT(2)))
 		;
 	/* read converted value */
 	value = STM32_ADC_DR;
@@ -249,12 +249,12 @@ int adc_enable_watchdog(int ch, int high, int low)
 	/* Clear flags */
 	STM32_ADC_ISR = 0x8e;
 	/* Set Watchdog enable bit on a single channel / continuous mode */
-	STM32_ADC_CFGR1 = (ch << 26) | (1 << 23) | (1 << 22)
-			|  (1 << 13) | (1 << 12);
+	STM32_ADC_CFGR1 = (ch << 26) | BIT(23) | BIT(22)
+			|  BIT(13) | BIT(12);
 	/* Enable watchdog interrupt */
-	STM32_ADC_IER = 1 << 7;
+	STM32_ADC_IER = BIT(7);
 	/* Start continuous conversion */
-	STM32_ADC_CR |= 1 << 2; /* ADSTART */
+	STM32_ADC_CR |= BIT(2); /* ADSTART */
 
 	return EC_SUCCESS;
 }
@@ -262,12 +262,12 @@ int adc_enable_watchdog(int ch, int high, int low)
 int adc_disable_watchdog(void)
 {
 	/* Stop on-going conversion */
-	STM32_ADC_CR |= 1 << 4; /* ADSTP */
+	STM32_ADC_CR |= BIT(4); /* ADSTP */
 	/* Wait for conversion to stop */
-	while (STM32_ADC_CR & (1 << 4))
+	while (STM32_ADC_CR & BIT(4))
 		;
 	/* CONT=0 -> continuous mode off / Clear Watchdog enable */
-	STM32_ADC_CFGR1 = 1 << 12;
+	STM32_ADC_CFGR1 = BIT(12);
 	/* Disable interrupt */
 	STM32_ADC_IER = 0;
 	/* Clear flags */
@@ -294,13 +294,13 @@ int adc_disable_watchdog(void)
 #define KEY2    0xCDEF89AB
 
 /* Lock bits for FLASH_CR register */
-#define PG       (1<<0)
-#define PER      (1<<1)
-#define OPTPG    (1<<4)
-#define OPTER    (1<<5)
-#define STRT     (1<<6)
-#define CR_LOCK  (1<<7)
-#define OPTWRE   (1<<9)
+#define PG       BIT(0)
+#define PER      BIT(1)
+#define OPTPG    BIT(4)
+#define OPTER    BIT(5)
+#define STRT     BIT(6)
+#define CR_LOCK  BIT(7)
+#define OPTWRE   BIT(9)
 
 int flash_physical_write(int offset, int size, const char *data)
 {
diff --git a/board/zinger/runtime.c b/board/zinger/runtime.c
index f92b919398..9e883888af 100644
--- a/board/zinger/runtime.c
+++ b/board/zinger/runtime.c
@@ -94,19 +94,19 @@ DECLARE_IRQ(STM32_IRQ_TIM2, tim2_interrupt, 1);
 static void zinger_config_hispeed_clock(void)
 {
 	/* Ensure that HSI8 is ON */
-	if (!(STM32_RCC_CR & (1 << 1))) {
+	if (!(STM32_RCC_CR & BIT(1))) {
 		/* Enable HSI */
-		STM32_RCC_CR |= 1 << 0;
+		STM32_RCC_CR |= BIT(0);
 		/* Wait for HSI to be ready */
-		while (!(STM32_RCC_CR & (1 << 1)))
+		while (!(STM32_RCC_CR & BIT(1)))
 			;
 	}
 	/* PLLSRC = HSI, PLLMUL = x12 (x HSI/2) = 48Mhz */
 	STM32_RCC_CFGR = 0x00288000;
 	/* Enable PLL */
-	STM32_RCC_CR |= 1 << 24;
+	STM32_RCC_CR |= BIT(24);
 	/* Wait for PLL to be ready */
-	while (!(STM32_RCC_CR & (1 << 25)))
+	while (!(STM32_RCC_CR & BIT(25)))
 			;
 
 	/* switch SYSCLK to PLL */
diff --git a/board/zinger/usb_pd_config.h b/board/zinger/usb_pd_config.h
index fbe24e0003..2a7e0e7f7d 100644
--- a/board/zinger/usb_pd_config.h
+++ b/board/zinger/usb_pd_config.h
@@ -47,7 +47,7 @@ static inline void spi_enable_clock(int port)
 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
 /* connect TIM3 CH1 to TIM3_CH2 input */
 #define TIM_CCR_CS  2
-#define EXTI_COMP_MASK(p) (1 << 7)
+#define EXTI_COMP_MASK(p) BIT(7)
 #define IRQ_COMP STM32_IRQ_EXTI4_15
 /* the RX is inverted, triggers on rising edge */
 #define EXTI_XTSR STM32_EXTI_RTSR
@@ -64,8 +64,8 @@ static inline void pd_set_pins_speed(int port)
 static inline void pd_tx_spi_reset(int port)
 {
 	/* Reset SPI1 */
-	STM32_RCC_APB2RSTR |= (1 << 12);
-	STM32_RCC_APB2RSTR &= ~(1 << 12);
+	STM32_RCC_APB2RSTR |= BIT(12);
+	STM32_RCC_APB2RSTR &= ~BIT(12);
 }
 
 /* Drive the CC line from the TX block */
@@ -81,7 +81,7 @@ static inline void pd_tx_enable(int port, int polarity)
 static inline void pd_tx_disable(int port, int polarity)
 {
 	/* Put TX GND (PA4) in Hi-Z state */
-	STM32_GPIO_BSRR(GPIO_A) = 1 << 4 /* Set */;
+	STM32_GPIO_BSRR(GPIO_A) = BIT(4) /* Set */;
 	/* Put SPI MISO (PA6) in Hi-Z by putting it in input mode  */
 	STM32_GPIO_MODER(GPIO_A) &= ~(0x3 << (2*6));
 }
diff --git a/board/zinger/usb_pd_policy.c b/board/zinger/usb_pd_policy.c
index c210ce9cea..07782c4f3b 100644
--- a/board/zinger/usb_pd_policy.c
+++ b/board/zinger/usb_pd_policy.c
@@ -70,7 +70,7 @@ static enum faults fault;
 static timestamp_t fault_deadline;
 
 /* ADC in 12-bit mode */
-#define ADC_SCALE (1 << 12)
+#define ADC_SCALE BIT(12)
 /* ADC power supply : VDDA = 3.3V */
 #define VDDA_MV   3300
 /* Current sense resistor : 5 milliOhm */