diff options
| author | Aseda Aboagye <aaboagye@google.com> | 2015-04-07 16:27:49 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-04-10 20:48:22 +0000 |
| commit | aa98b2dca53c5b8680a3dffc5d79ba95cc798fd8 (patch) | |
| tree | 6359bbf400691f5791db784bb562d8309a0a492e /board | |
| parent | 50bea9d35f14aacaeb13bfc545f6a93f7ddf64a4 (diff) | |
| download | chrome-ec-aa98b2dca53c5b8680a3dffc5d79ba95cc798fd8.tar.gz | |
snow: Move interrupt enabled gpios to top
All GPIOs with interrupt handlers should be together at the top of the gpio.inc
file.
BUG=none
BRANCH=none
TEST=make -j buildall
Change-Id: I6810a793cc16c38c8dde86f9cbec57a3f82aebfc
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/264504
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'board')
| -rw-r--r-- | board/snow/gpio.inc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/board/snow/gpio.inc b/board/snow/gpio.inc index 194c0d6f06..ea49c0b812 100644 --- a/board/snow/gpio.inc +++ b/board/snow/gpio.inc @@ -12,7 +12,7 @@ GPIO(SOC1V8_XPSHOLD, A, 3, GPIO_INT_BOTH, power_signal_interrupt) /* App Pr GPIO(CHARGER_INT_L, C, 4, GPIO_INT_FALLING, pmu_irq_handler) GPIO(LID_OPEN, C, 13, GPIO_INT_BOTH, lid_interrupt) /* LID switch detection */ GPIO(SUSPEND_L, A, 7, INT_BOTH_FLOATING, power_signal_interrupt) /* AP suspend/resume state */ -GPIO(WP_L, B, 4, GPIO_INPUT, NULL) /* Write protection pin (low active) */ +GPIO(SPI1_NSS, A, 4, GPIO_DEFAULT, spi_event) /* Keyboard inputs */ GPIO(KB_IN00, C, 8, GPIO_KB_INPUT, keyboard_raw_gpio_interrupt) @@ -24,9 +24,10 @@ GPIO(KB_IN05, C, 14, GPIO_KB_INPUT, keyboard_raw_gpio_interrupt) GPIO(KB_IN06, C, 15, GPIO_KB_INPUT, keyboard_raw_gpio_interrupt) GPIO(KB_IN07, D, 2, GPIO_KB_INPUT, keyboard_raw_gpio_interrupt) + /* Other inputs */ GPIO(AC_PWRBTN_L, A, 0, GPIO_INT_BOTH, NULL) -GPIO(SPI1_NSS, A, 4, GPIO_DEFAULT, spi_event) +GPIO(WP_L, B, 4, GPIO_INPUT, NULL) /* Write protection pin (low active) */ /* * I2C pins should be configured as inputs until I2C module is |