diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-05-24 10:49:27 -0500 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-05-24 15:46:02 -0700 |
| commit | 90b934d4e95c3ac8f100fc2447ff3c51960ff268 (patch) | |
| tree | 3f632140af90dc716697ea656cd08fbde14abef6 /board | |
| parent | c8a49484176144dfd5d99969a74af3aba27a8e5a (diff) | |
| download | chrome-ec-90b934d4e95c3ac8f100fc2447ff3c51960ff268.tar.gz | |
reef: keep analogix pd chip in reset
The gpio settings for the USB_PD_RST_ODL signal had the default
state high while the power enable, EN_USB_TCPC_PWR, was low. This
is combination of settings is invalid for the part. Therefore,
keep USB_PD_RST_ODL low until board_set_tcpc_power_mode() is called
to bring the pd chip online.
BUG=chrome-os-partner:53035
BRANCH=None
TEST=Rachel confirmed things still working.
Change-Id: I8b6b54a474c00165a4d0af944fb60f2923b9ef5c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347000
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'board')
| -rw-r--r-- | board/reef/gpio.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/reef/gpio.inc b/board/reef/gpio.inc index 187739a77a..81db6177d0 100644 --- a/board/reef/gpio.inc +++ b/board/reef/gpio.inc @@ -109,7 +109,7 @@ GPIO(PCH_RCIN_L, PIN(6, 1), GPIO_ODR_HIGH) /* SYS_RST_ODL */ GPIO(CHARGER_RST_ODL, PIN(C, 0), GPIO_ODR_HIGH) GPIO(USB_A_CHARGE_EN_L, PIN(4, 2), GPIO_OUT_HIGH) GPIO(EN_USB_TCPC_PWR, PIN(C, 3), GPIO_OUT_LOW) -GPIO(USB_PD_RST_ODL, PIN(0, 3), GPIO_ODR_HIGH) +GPIO(USB_PD_RST_ODL, PIN(0, 3), GPIO_ODR_LOW) GPIO(EN_USB_A_5V, PIN(4, 1), GPIO_OUT_LOW) GPIO(USB_C0_5V_EN, PIN(D, 3), GPIO_OUT_LOW) /* EN_USB_CN_5V_OUT, Enable C0 */ GPIO(USB_C1_5V_EN, PIN(B, 1), GPIO_OUT_LOW) /* EN_USB_C1_5V_OUT, Enable C1 */ |