diff options
| author | Devin Lu <devin.lu@quantatw.com> | 2019-12-09 22:29:46 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-12-11 03:40:19 +0000 |
| commit | 29fdf0d429bbe5272a6e560852feb8a71c7dc957 (patch) | |
| tree | ac1a3d5b039361603023768c120de2736064deaa /board | |
| parent | 0d300a80616e5669ad43269c2dfc913f9feedf12 (diff) | |
| download | chrome-ec-29fdf0d429bbe5272a6e560852feb8a71c7dc957.tar.gz | |
jinlon: Make sure EC_RST_ODL is GPIO_LOCKED
Clone from CL:1928422
BUG=none
BRANCH=hatch
TEST=make buildall
Change-Id: I488ecaa317b2164d693c9acea2ed010da2e26e2b
Signed-off-by: Devin Lu <Devin.Lu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1958386
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Diffstat (limited to 'board')
| -rw-r--r-- | board/jinlon/gpio.inc | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/board/jinlon/gpio.inc b/board/jinlon/gpio.inc index 21be5fd334..99661cae46 100644 --- a/board/jinlon/gpio.inc +++ b/board/jinlon/gpio.inc @@ -61,6 +61,17 @@ GPIO(CPU_C10_GATE_L, PIN(6, 7), GPIO_INPUT) /* MKBP event synchronization */ GPIO(EC_INT_L, PIN(7, 0), GPIO_ODR_HIGH) +/* + * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an + * interrupt handler because it is automatically handled by the PSL. + * + * We need to lock the setting so this gpio can't be reconfigured to overdrive + * the real reset signal. (This is the PSL input pin not the real reset pin). + */ +GPIO(EC_RST_ODL, PIN(0, 2), GPIO_INT_BOTH | + GPIO_HIB_WAKE_HIGH | + GPIO_LOCKED) + /* USB and USBC Signals */ GPIO(USB_C_OC_ODL, PIN(B, 1), GPIO_ODR_HIGH) GPIO(USB_C0_TCPC_RST_ODL, PIN(9, 7), GPIO_ODR_HIGH) |