diff options
author | Craig Hesling <hesling@chromium.org> | 2019-12-04 20:04:27 -0800 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2019-12-12 00:11:03 +0000 |
commit | 40b6c5de590e6290e6b516c380f6b59efbff4fa3 (patch) | |
tree | f026db50fdef672ff4055d2a8cd2d7774496d134 /board | |
parent | 92e1c8698ab44582e329ccdea0e50dd9012116fa (diff) | |
download | chrome-ec-40b6c5de590e6290e6b516c380f6b59efbff4fa3.tar.gz |
board: Add nucleo-h743zi
This brings initial support for the Nucleo-H743ZI
development board.
This configuration is similar to nocturne_fp, but without
fingerprint sensor support, without rollback secret
support, and with an adjusted console USART selection.
The included README.md shows some quick steps to
get a Nucleo-H743ZI up and running EC.
Note that the RSA key included is only for test builds.
It should not be used for any production builds.
BRANCH=none
BUG=none
TEST=make BOARD=nucleo-h743zi
make BOARD=nucleo-h743zi flash
minicom -D/dev/ttyACM0
Change-Id: Ibe4b19e51467831f53365a0a7f52bec3d854f806
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1952290
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'board')
-rw-r--r-- | board/nucleo-h743zi/README.md | 85 | ||||
-rw-r--r-- | board/nucleo-h743zi/board.c | 64 | ||||
-rw-r--r-- | board/nucleo-h743zi/board.h | 199 | ||||
-rw-r--r-- | board/nucleo-h743zi/build.mk | 15 | ||||
-rw-r--r-- | board/nucleo-h743zi/dev_key.pem | 39 | ||||
-rw-r--r-- | board/nucleo-h743zi/ec.tasklist | 13 | ||||
-rw-r--r-- | board/nucleo-h743zi/gpio.inc | 23 | ||||
-rw-r--r-- | board/nucleo-h743zi/openocd-flash.cfg | 14 | ||||
-rw-r--r-- | board/nucleo-h743zi/openocd.cfg | 9 |
9 files changed, 461 insertions, 0 deletions
diff --git a/board/nucleo-h743zi/README.md b/board/nucleo-h743zi/README.md new file mode 100644 index 0000000000..58d47219da --- /dev/null +++ b/board/nucleo-h743zi/README.md @@ -0,0 +1,85 @@ +# Nucleo H743ZI + +This is a simpler EC example for the ST Nucleo H743ZI +development board. + +# Quick Start + +The Nucleo dev boards have lots of developer friendly features, +like an in-circuit debugger/programmer/UART-bridge, programmable +LEDs, and a button, to name a few. + +The built-in debugger can be connected to using a Micro USB cable. +It provides three great interfaces to the host. +1. Mass storage interface for drag-drop programming +2. Full ST-Link in-circuit debugger +3. UART bridge for logs/consoles + +We will use a few of these interfaces below to program and interact +with out Nucleo dev board. + +## Build + +```bash +make BOARD=nucleo-h743zi -j +``` + +## Program + +The easiest way to flash the Nucleo board is to Copy-Paste/Drag-Drop +the firmware image onto the exposed mass storage drive. + +Open a file browser and `Copy` the file in `build/nucleo-h743zi/ec.bin`. +Now, find the removable storage that the Nucleo device has presented, +and `Paste` the file into the directory. + +## Interact + +After the Nucelo finishes programming, you can open the EC console. +On GNU/Linux, this is mapped to `/dev/ttyACM0`. + +Install `minicom` and issue the following command: + +```bash +minicom -D/dev/ttyACM0 +``` + +# Unit Testing + +A fun EC feature is that unit tests can be run on-device. + +This is made possible by an alternative build rule that generates a +test image per unit test. These test images use a unit test specific taskset +and console command to trigger them. + +## Create + +To enable an existing unit test, add it to the [build.mk](build.mk)'s +`test-list-y` variable. + +See the main [README.md](/README.md) on how to write a new unit test. + +## Build + +To build all unit test images for this board, run the following command: + +```bash +make BOARD=nucleo-h743zi tests +``` + +You can build a specific unit test image by changing `tests` to `test-aes`, +for the `aes` unit test. + +## Flash + +Copy/paste the `build/nucleo-h743zi/${TEST}/${TEST}.bin` file to the +Nucleo's mass storage drive, where `${TEST}` is the name of the unit test, +like `aes`. + +## Run + +1. Connect to UART console + ```bash + minicom -D/dev/ttyACM0 + ``` +2. Run the `runtest` command
\ No newline at end of file diff --git a/board/nucleo-h743zi/board.c b/board/nucleo-h743zi/board.c new file mode 100644 index 0000000000..f07be9d78b --- /dev/null +++ b/board/nucleo-h743zi/board.c @@ -0,0 +1,64 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" +#include "console.h" +#include "gpio.h" +#include "hooks.h" +#include "registers.h" +#include "spi.h" +#include "system.h" +#include "task.h" +#include "util.h" + +/** + * Disable restricted commands when the system is locked. + * + * @see console.h system.c + */ +int console_is_restricted(void) +{ + return system_is_locked(); +} + +static void ap_deferred(void) +{ + /* + * in S3: SLP_S3_L is 0 and SLP_S0_L is X. + * in S0ix: SLP_S3_L is X and SLP_S0_L is 0. + * in S0: SLP_S3_L is 1 and SLP_S0_L is 1. + * in S5/G3, the FP MCU should not be running. + */ + int running = gpio_get_level(GPIO_PCH_SLP_S3_L) + && gpio_get_level(GPIO_PCH_SLP_S0_L); + + if (running) { /* S0 */ + disable_sleep(SLEEP_MASK_AP_RUN); + hook_notify(HOOK_CHIPSET_RESUME); + } else { /* S0ix/S3 */ + hook_notify(HOOK_CHIPSET_SUSPEND); + enable_sleep(SLEEP_MASK_AP_RUN); + } +} +DECLARE_DEFERRED(ap_deferred); + +/* PCH power state changes */ +void slp_event(enum gpio_signal signal) +{ + hook_call_deferred(&ap_deferred_data, 0); +} + +#include "gpio_list.h" + +/* Initialize board. */ +static void board_init(void) +{ + /* Enable interrupt on PCH power signals */ + gpio_enable_interrupt(GPIO_PCH_SLP_S3_L); + gpio_enable_interrupt(GPIO_PCH_SLP_S0_L); + /* enable the SPI slave interface if the PCH is up */ + hook_call_deferred(&ap_deferred_data, 0); +} +DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); diff --git a/board/nucleo-h743zi/board.h b/board/nucleo-h743zi/board.h new file mode 100644 index 0000000000..435b8a444b --- /dev/null +++ b/board/nucleo-h743zi/board.h @@ -0,0 +1,199 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * STM32H743 MCU configuration + */ + +#ifndef __BOARD_H +#define __BOARD_H + +#undef CONFIG_SYSTEM_UNLOCKED + +/* + * Flash layout: + * + * +++++++++++++ + * | RO | Bank 1 + * | | + * | | + * | ......... | + * | Rollback | (last two sectors) + * +-----------+ + * | RW | Bank 2 + * | | + * | | + * | | + * | | + * +++++++++++++ + * + * We adjust the following macros to accommodate a rollback region + * and RO/RW regions of different sizes. + */ + +#undef _IMAGE_SIZE +#undef CONFIG_ROLLBACK_OFF +#undef CONFIG_ROLLBACK_SIZE +#undef CONFIG_FLASH_PSTATE +#undef CONFIG_FW_PSTATE_SIZE +#undef CONFIG_FW_PSTATE_OFF +#undef CONFIG_RO_MEM_OFF +#undef CONFIG_RO_STORAGE_OFF +#undef CONFIG_RO_SIZE +#undef CONFIG_RW_MEM_OFF +#undef CONFIG_RW_STORAGE_OFF +#undef CONFIG_RW_SIZE +#undef CONFIG_EC_PROTECTED_STORAGE_OFF +#undef CONFIG_EC_PROTECTED_STORAGE_SIZE +#undef CONFIG_EC_WRITABLE_STORAGE_OFF +#undef CONFIG_EC_WRITABLE_STORAGE_SIZE +#undef CONFIG_WP_STORAGE_OFF +#undef CONFIG_WP_STORAGE_SIZE + +/* + * EC rollback protection block + * + * We need 2 independently erasable blocks, at a minimum. + */ +#define CONFIG_ROLLBACK_SIZE (2 * CONFIG_FLASH_BANK_SIZE) +#define CONFIG_ROLLBACK_OFF ((CONFIG_FLASH_SIZE / 2) - CONFIG_ROLLBACK_SIZE) + +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_SIZE CONFIG_ROLLBACK_OFF +#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE / 2) +#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE / 2) + +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RW_STORAGE_OFF 0 + +#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE + +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE + +/* Disabled features */ + +#undef CONFIG_ADC +#undef CONFIG_HIBERNATE +#undef CONFIG_I2C +#undef CONFIG_LID_SWITCH +#undef CONFIG_TASK_PROFILING + +/* Enabled features */ + +#define CONFIG_AES +#define CONFIG_AES_GCM +#define CONFIG_DMA +#define CONFIG_FORCE_CONSOLE_RESUME +#define CONFIG_FPU +#define CONFIG_HOST_COMMAND_STATUS +#define CONFIG_LOW_POWER_IDLE +#define CONFIG_MKBP_EVENT +#define CONFIG_MKBP_USE_GPIO +#define CONFIG_PRINTF_LEGACY_LI_FORMAT +#define CONFIG_RNG +#define CONFIG_RWSIG_TYPE_RWSIG +#define CONFIG_SHA256 +#define CONFIG_SHA256_UNROLLED +#undef CONFIG_SHAREDLIB_SIZE +#define CONFIG_SHAREDLIB_SIZE 0 +#define CONFIG_STM_HWTIMER32 +#define CONFIG_SUPPRESSED_HOST_COMMANDS \ + EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_PD_GET_LOG_ENTRY +#define CONFIG_WATCHDOG_HELP +#define CONFIG_WP_ACTIVE_HIGH + +#ifndef TEST_BUILD + /* TODO(hesling): Fix the illogical dependency between spi.c + * and host_command.c + * + * Currently, the chip/stm32/spi.c depends on functions defined in + * common/host_command.c. When unit test builds use their own tasklist + * without the HOSTCMD task, host_command.c is excluded from the build, + * but chip/stm32/spi.c remains (because of CONFIG_SPI). + * This triggers an undefined reference linker error. + * The reproduce case: + * - Allow CONFIG_SPI in TEST_BUILDs + * - make BOARD=nucleo-h743zi tests + */ +# define CONFIG_SPI +#endif + +/* + * We want to prevent flash readout, and use it as indicator of protection + * status. + */ +#define CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE + +/* + * RW does slow compute, RO does slow flash erase. + */ +#undef CONFIG_WATCHDOG_PERIOD_MS +#define CONFIG_WATCHDOG_PERIOD_MS 10000 + +/* + * These allow console commands to be flagged as restricted. + * Restricted commands will only be permitted to run when + * console_is_restricted() returns false. + * See console_is_restricted's definition in board.c. + */ +#define CONFIG_CONSOLE_COMMAND_FLAGS +#define CONFIG_RESTRICTED_CONSOLE_COMMANDS + +/* Setup UART console */ + +#undef CONFIG_UART_CONSOLE +#define CONFIG_UART_CONSOLE 3 /* The UART console is on USART3 */ +#define CONFIG_UART_TX_DMA +#define CONFIG_UART_TX_DMA_PH DMAMUX1_REQ_USART3_TX +#undef CONFIG_UART_TX_BUF_SIZE +#define CONFIG_UART_TX_BUF_SIZE 2048 + +/* Console commands */ + +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_IDLE_STATS + +#ifdef SECTION_IS_RW + /* + * Use the malloc code only in the RW section (for the private library), + * we cannot enable it in RO since it is not compatible with the + * RW verification (shared_mem_init done too late). + */ +# define CONFIG_MALLOC +#else /* !SECTION_IS_RW */ + /* RO verifies the RW partition signature */ +# define CONFIG_RSA +# define CONFIG_RSA_KEY_SIZE 3072 +# define CONFIG_RSA_EXPONENT_3 +# define CONFIG_RWSIG +#endif /* SECTION_IS_RW */ + +/* + * We do not use any "locally" generated entropy: this is normally used + * to add local entropy when the main source of entropy is remote. + */ +#undef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE +#ifdef SECTION_IS_RW +# undef CONFIG_ROLLBACK_UPDATE +#endif +/* + * Add rollback protection + */ +#define CONFIG_ROLLBACK +#define CONFIG_ROLLBACK_MPU_PROTECT + +#ifndef __ASSEMBLER__ + /* Timer selection */ +# define TIM_CLOCK32 2 +# define TIM_WATCHDOG 16 + +# include "gpio_signal.h" +#endif /* !__ASSEMBLER__ */ + +#endif /* __BOARD_H */ diff --git a/board/nucleo-h743zi/build.mk b/board/nucleo-h743zi/build.mk new file mode 100644 index 0000000000..6a912763db --- /dev/null +++ b/board/nucleo-h743zi/build.mk @@ -0,0 +1,15 @@ +# Copyright 2019 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Board specific files build + +# the IC is STmicro STM32H743 +CHIP:=stm32 +CHIP_FAMILY:=stm32h7 +CHIP_VARIANT:=stm32h7x3 + +board-y=board.o + +# Enable on device tests +test-list-y=aes sha256 sha256_unrolled diff --git a/board/nucleo-h743zi/dev_key.pem b/board/nucleo-h743zi/dev_key.pem new file mode 100644 index 0000000000..cb402c9c68 --- /dev/null +++ b/board/nucleo-h743zi/dev_key.pem @@ -0,0 +1,39 @@ +-----BEGIN RSA PRIVATE KEY----- +MIIG4wIBAAKCAYEAnWlGtHyWlAntpuFtoK4ukTuqnvaPiZrr7I8S+9cVpwGJXa7A +yqK5bp8kmZiUDZEMpFA6+f6OGT8dOS5e07vUcIPaZXc1tbaXADywqI04BdCgPsPP +pKNnKSUglkkgH2WQ/3aqPrT8IJ17+rCUNLysbvcNy3g0CAj0BGzY/s/2mn50C155 +R+6FsQ47jfBS1vOm3s6bOik73VZMutUyBXu5+Sy6HS0kiuAuL3g9tgslqlVaPWS/ +B6+Pd2ednqTp027z9ZJiY40OdXsTzqoD5iwkkcA391thkfsYASVloLplfFtbymWM +QaqGyaXeuXmeVXr5NUvpeLwgpA1/spX6BfBhmEK/yJ2FeYaKoBWSLz3UztZMG/FK +glupYLcV3FTJ6zHzy0LOqsdIZKpQivazHfTD5HsKuokNDZVQjtn+Oga8LWEAA8TQ +ZB+vEpYxSxi2AHwSjEQaXv8dBgnyTl173qFy4RlZ3d9qpZP3bntVpMGQlIjuYAIM +cbKoLO69rEED+zr7AgEDAoIBgGjw2c2oZGKxSRnrnmseybYnxxSkX7ER8p20t1KP +Y8SrsOkfKzHB0PRqGGZluAkLXcLgJ1FUXrt/aNDJlI0n4vWtPEOkznkkZKrTIHBe +JVk1wCnX38MXmhtuFbmGFWpDtf+kcX8jUsBo/VHLDXh9yEn6CTJQIrAF+ALzO1SK +pGb++AeUUNqfA8te0l6gNzn3xJSJvNFw0pOO3dHjdq5Se/tzJr4eGFyVdB+lfnlc +w8bjkX5DKgUftPpFE78Ym+JJ9u1XgVtetZBUAeVl39X+cZZZHXIIu84JtF23qb77 +iHJa85zWKqBXChg3aOReLbbF1tg+HPATDzlXPk0wq9l+HEERkkM7WdsjlBtH/so6 +euQ5mGE8vx/TaggY4gBtVjvsgKe89bzxmIGhLMdKjmwZOYqZKNd4ZujPfj8Mh9cu +LCsjEwv1WgXBoSI+vDEscV9aSjEU/AkWryc/k/Zo0wfYjRF5+faw9csAl3NSGwOs +hCiWya8+2z390d+Sc3k3FUH/awKBwQDMq/VieSR08kpSvbakKqxvamrCfeJ0qHA4 +H0scQgVwAwNaFAZptJwdACHNj/XS+AkIWG4ycLL/o2PvbOvcQMJ+2ga0j1iFLixJ +uFaMi7sUJKIe7+5/cqtoFWhfW3wRildjBRXKxf4GBYrn6eMUjlxSs8pY/j2eLqEc +zTJzzYoFffI54Ck/tyry0JJR6Jv5hAxS4Acu/ip2zf20lfTOM8Kvt1jYJ4S6Nc1n +pkx7RUmroALms20u3qZHBu45Pe2FWlECgcEAxOMq+AXZqArGo9N9gQPNwNAhCdBl +aEQZPHKb5f8TYM/rBRBF53NbiFKflVxj8Fot6JZP3i7Wzmc+T2AMY3J0t85drzUm +K6MALXE9c1phZFtFayY9Uyve7HxafFVMf8TbbKJIRJblnDMCeBz6Z0CRQeGDHlY1 +Ei9yE3oAA3Pv5y5xN/SgG8YSbGeEr21v9/CW78SZIl7r1FyWqCpKhKjclysKE651 +Ot1G2dngo/mArAa88nBWZddHFowiPTB2kuGLAoHBAIhyo5b7baNMMYx+ecLHHZ+c +RyxT7E3FoCVqMhLWrkqsrOa4BEZ4aBNVa95f+TdQBgWQSXb1zKps7UpInT2Aganm +ryMKOwN0HYZ65F2yfLgYbBSf9FT3HPAORZTnqAuxj5dYuTHZVAQDse/xQg20PYx3 +3DtUKRQfFhMzdvfeXAOpTCaVcNUkx0yLDDabEqZYCDdABMn+xvneqSMOozQigcp6 +OzrFAybOiO/EMvzY28fAAe8iSMnpxC9Z9CYpSQORiwKBwQCDQhylWTvFXIRtN6kA +rTPV4BYGiu5Fgrt9ob1D/2JAipyuCtlE95Ja4b+46EKgPB6bDt/pdI80RNQ06rLs +9vh6iZPKI27HwgAeS35M5uuYPNjyGX43cpSdqDxS44hVLeedwYWDD0O9d1b6vfxE +1bYr66y+5CNhdPa3pqqs9/VEyaDP+Gq9Lrby763KSPVP9bn1LbtsP0fi6GRwHDGt +xehkx1wNHvjR6NnmkUBtUQByryihoDmZOi9kXWwoyvm3QQcCgcEAw8zqXhE7phhN +WZZeYjZYYC295VQxktUM7RT2ld2wnE6sFKrBBPtipgZC9o5bgajjNOUQEmkoGkw0 ++TzUwrrB3awzAh9+83XVtT1BiQP3rDdBXuWPnHEe5v/7Zzg06YHfxVOi0WlohqoV +RrUsbxLRn83Z+5HhhRlIKEuUq5cIkPR/QJDyxNfxmykC9eS7LrAdaBU9dDF6uZYI +6mxZaz6MAmYRNlFyQA3BMBJIcykQU10Jxil68yOrYLz7o1zARFxZ +-----END RSA PRIVATE KEY----- diff --git a/board/nucleo-h743zi/ec.tasklist b/board/nucleo-h743zi/ec.tasklist new file mode 100644 index 0000000000..ec42cd45eb --- /dev/null +++ b/board/nucleo-h743zi/ec.tasklist @@ -0,0 +1,13 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/** + * See CONFIG_TASK_LIST in config.h for details. + */ +#define CONFIG_TASK_LIST \ + TASK_ALWAYS_RO(RWSIG, rwsig_task, NULL, 1280) \ + TASK_ALWAYS(HOOKS, hook_task, NULL, 1024) \ + TASK_NOTEST(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) diff --git a/board/nucleo-h743zi/gpio.inc b/board/nucleo-h743zi/gpio.inc new file mode 100644 index 0000000000..188b7c14de --- /dev/null +++ b/board/nucleo-h743zi/gpio.inc @@ -0,0 +1,23 @@ +/* + * Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Interrupts */ +GPIO_INT(SPI1_NSS, PIN(A, 4), GPIO_INPUT, spi_event) + +GPIO_INT(PCH_SLP_S0_L, PIN(D,13), GPIO_INT_BOTH, slp_event) +GPIO_INT(PCH_SLP_S3_L, PIN(A,11), GPIO_INT_BOTH, slp_event) + +GPIO(WP, PIN(B, 7), GPIO_INPUT) + +/* Outputs */ +GPIO(EC_INT_L, PIN(A, 1), GPIO_OUT_HIGH) + +UNIMPLEMENTED(ENTERING_RW) + +/* USART3: PD8/PD9 */ +ALTERNATE(PIN_MASK(D, 0x0300), GPIO_ALT_USART, MODULE_UART, GPIO_PULL_UP) +/* SPI1 slave from the AP: PA4/5/6/7 */ +ALTERNATE(PIN_MASK(A, 0x00f0), GPIO_ALT_SPI, MODULE_SPI, 0) diff --git a/board/nucleo-h743zi/openocd-flash.cfg b/board/nucleo-h743zi/openocd-flash.cfg new file mode 100644 index 0000000000..4517266d7b --- /dev/null +++ b/board/nucleo-h743zi/openocd-flash.cfg @@ -0,0 +1,14 @@ +# Copyright 2019 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +source [find board/st_nucleo_h743zi.cfg] + +gdb_port 0 +tcl_port 0 +telnet_port 0 +init +reset halt +flash write_image erase $BUILD_DIR/ec.bin 0x08000000 +reset +shutdown diff --git a/board/nucleo-h743zi/openocd.cfg b/board/nucleo-h743zi/openocd.cfg new file mode 100644 index 0000000000..528e8d6cab --- /dev/null +++ b/board/nucleo-h743zi/openocd.cfg @@ -0,0 +1,9 @@ +# Copyright 2019 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +source [find board/st_nucleo_h743zi.cfg] + +# Enabled EC task context support +# This is supported by the upstream OpenOCD +$_TARGETNAME configure -rtos Chromium-EC |