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| author | Vadim Bendebury <vbendeb@chromium.org> | 2015-11-06 10:59:33 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-11-10 06:54:43 -0800 |
| commit | 62691cac030c4f0bd350a086e4b182673730d64c (patch) | |
| tree | f9a8f6d6708814a9f85e610edf08bb184e833322 /chip/g/config_chip.h | |
| parent | b895b9e933714f17b24f9f080b20ea4e62c124dc (diff) | |
| download | chrome-ec-62691cac030c4f0bd350a086e4b182673730d64c.tar.gz | |
cr50: make customized RO work
This patch completes introduction of building of proper RO and RW
images for cr50.
A few small mods were required:
- both RO and RW images have to be signed, using the same dedicated
signer, but with different keys, dev_key.pem is not needed any more.
- the RW image offset is not at the half of available flash, a chip
specific value of 16K is used instead.
The suggested new image layout is as follows:
+----------------------------------------+
| 1KB RO signature header. |
+----------------------------------------+
- -
| 15KB RO image. |
- -
+========================================+
| 1KB RW-A signature header. |
+----------------------------------------+
- -
- -
| 239K RW-A image. |
- -
- -
+========================================+
- -
| 16 KB NVRAM, shared |
- -
+========================================+
| 1KB RW-B signature header. |
+----------------------------------------+
- -
- -
| 239K RW-B image. |
- -
- -
+========================================+
BRANCH=none
BUG=chrome-os-partner:43025
TEST=The combined image (build/cr50/ec.hex) is successfully loaded and
started by the spiflash utility from the latest FPGA tarball.
Corrupting a byte in the generated image in the RW section causes
failure to verify.
Change-Id: I41a05168b0d4e9f88efa1003f261b6dd03972a24
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311422
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Diffstat (limited to 'chip/g/config_chip.h')
| -rw-r--r-- | chip/g/config_chip.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/chip/g/config_chip.h b/chip/g/config_chip.h index 1818fbce60..3978371a26 100644 --- a/chip/g/config_chip.h +++ b/chip/g/config_chip.h @@ -64,4 +64,11 @@ /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT (GC_INTERRUPTS_COUNT - 16) +#undef CONFIG_RW_MEM_OFF + +/* Leaving 16K for the RO aka loader. */ +#define CONFIG_RW_MEM_OFF 0x4000 + +#define CONFIG_CUSTOMIZED_RO + #endif /* __CROS_EC_CONFIG_CHIP_H */ |