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| author | Bill Richardson <wfrichar@chromium.org> | 2016-07-24 23:58:05 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-07-26 12:27:33 -0700 |
| commit | 20a6d75aee99c50a1646b73e11e7bb84276439c6 (patch) | |
| tree | 9588552acafe7f29da2f3c3622c0207337d42659 /chip/g/config_chip.h | |
| parent | 0564276033dd2615b95fa3f85152b9cc56c166d3 (diff) | |
| download | chrome-ec-20a6d75aee99c50a1646b73e11e7bb84276439c6.tar.gz | |
g: Improve version info for dual RO & RW images
The SoC looks for two RO images at reset, and is typically
configured for two RW images as well. This CL reports version
strings for all those images, as well as identifying the active
RO and RW copies.
Since the RO image doesn't contain a version string, we create
one using the epoch_, major_, minor_, and img_chk_ members of its
signed header.
BUG=chrome-os-partner:55558
BRANCH=none
TEST=make buildall; run on Cr50 hardware
The "version" command now includes information like this:
RO_A: * 0.0.2/a3c3d5ea
RO_B: 0.0.2/8895c9eb
RW_A: cr50_v1.1.4965-a6c1c73-dirty
RW_B: * cr50_v1.1.4959-2f49d5c
The '*' indicates the active image.
The test/tpm_test/tpmtest.py program has been updated to request
the version information at startup, and it also now reports
similar information, just all on one line:
RO_A:* 0.0.2/a3c3d5ea RO_B: 0.0.2/8895c9eb RW_A: cr50_v1.1 ...
The active images are marked with a '*' following the ':', so
that the same regexp can match either format:
($ro, $rw) = m/RO_[AB]:\s*\*\s+(\S+).*RW_[AB]:\s*\*\s+(\S+)/s;
Change-Id: Ic27e295d9122045b2ec5a638933924b65ecc8e43
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362861
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Diffstat (limited to 'chip/g/config_chip.h')
| -rw-r--r-- | chip/g/config_chip.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/chip/g/config_chip.h b/chip/g/config_chip.h index 99b9195b8b..97cc56ba94 100644 --- a/chip/g/config_chip.h +++ b/chip/g/config_chip.h @@ -81,6 +81,9 @@ * The following macros try to make this all work. */ +/* This isn't optional, since the bootrom will always look for both */ +#define CHIP_HAS_RO_B + /* It's easier for us to consider each half as having its own RO and RW */ #define CFG_FLASH_HALF (CONFIG_FLASH_SIZE >> 1) @@ -96,11 +99,15 @@ /* The RO images start at the very beginning of each flash half */ #define CONFIG_RO_MEM_OFF 0 +#define CHIP_RO_B_MEM_OFF CFG_FLASH_HALF /* Size reserved for each RO image */ #define CONFIG_RO_SIZE 0x4000 -/* RW images start right after the reserved-for-RO areas in each half */ +/* + * RW images start right after the reserved-for-RO areas in each half, but only + * because that's where the RO images look for them. It's not a HW constraint. + */ #define CONFIG_RW_MEM_OFF CONFIG_RO_SIZE #define CONFIG_RW_B_MEM_OFF (CFG_FLASH_HALF + CONFIG_RW_MEM_OFF) |