Cr50: Add support for flash write & erase

This adds flash support for the SoC.

BUG=chrome-os-partner:44745
BRANCH=none
TEST=manual

Pick an unused section of flash and use the flasherase and
flashwrite commands to test it. The flashwrite command fills a
buffer with bytes, counting up (0x00, 0x01, 0x02, 0x03, ...),
then writes that buffer to the address given.

Note that the "md" command uses the absolute address, while the
flash commands use the offset address within the flash memory.

For example:

Test bank 0:

  > md 0x7b000 16

  0007B000: 00000000 00000000 00000000 00000000
  0007B010: 00000000 00000000 00000000 00000000
  0007B020: 00000000 00000000 00000000 00000000
  0007B030: 00000000 00000000 00000000 00000000

  > flasherase 0x3b000 0x800
  Erasing 2048 bytes at 0x3b000...

  > md 0x7b000 16

  0007B000: ffffffff ffffffff ffffffff ffffffff
  0007B010: ffffffff ffffffff ffffffff ffffffff
  0007B020: ffffffff ffffffff ffffffff ffffffff
  0007B030: ffffffff ffffffff ffffffff ffffffff
  >

  > flashwrite 0x3b000 0x800
  Writing 2048 bytes to 0x3b000...

  > md 0x7b000 16

  0007B000: 03020100 07060504 0b0a0908 0f0e0d0c
  0007B010: 13121110 17161514 1b1a1918 1f1e1d1c
  0007B020: 23222120 27262524 2b2a2928 2f2e2d2c
  0007B030: 33323130 37363534 3b3a3938 3f3e3d3c

  > md .b 0x7b000 16

  0007B000: 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f

Test bank 1:

  > md 0xbb000 16

  000BB000: ffffffff ffffffff ffffffff ffffffff
  000BB010: ffffffff ffffffff ffffffff ffffffff
  000BB020: ffffffff ffffffff ffffffff ffffffff
  000BB030: ffffffff ffffffff ffffffff ffffffff

  > flasherase 0x7b000 0x800
  Erasing 2048 bytes at 0x7b000...

  > md 0xbb000 16

  000BB000: ffffffff ffffffff ffffffff ffffffff
  000BB010: ffffffff ffffffff ffffffff ffffffff
  000BB020: ffffffff ffffffff ffffffff ffffffff
  000BB030: ffffffff ffffffff ffffffff ffffffff

  > flashwrite 0x7b000 0x800
  Writing 2048 bytes to 0x7b000...

  > md 0xbb000 16

  000BB000: 03020100 07060504 0b0a0908 0f0e0d0c
  000BB010: 13121110 17161514 1b1a1918 1f1e1d1c
  000BB020: 23222120 27262524 2b2a2928 2f2e2d2c
  000BB030: 33323130 37363534 3b3a3938 3f3e3d3c

  > md .b 0xbb000 16

  000BB000: 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
  >

Change-Id: I956e813871949faed8d85ad9e46bdc64dee1a9e9
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/299757

1 files changed, 9 insertions, 6 deletions

diff --git a/chip/g/config_chip.h b/chip/g/config_chip.h
index c2a75ce030..149fea8c34 100644
--- a/chip/g/config_chip.h
+++ b/chip/g/config_chip.h
@@ -17,14 +17,17 @@
 #define CONFIG_RAM_SIZE         0x10000
 
 /* Flash chip specifics */
-#define CONFIG_FLASH_BANK_SIZE      0x00000800  /* protect bank size */
-#define CONFIG_FLASH_ERASE_SIZE     0x00000400  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE     0x00000004  /* minimum write size */
-#define CONFIG_RO_HEAD_ROOM	    1024	/* Room for ROM signature. */
+#define CONFIG_FLASH_BANK_SIZE         0x800	/* protect bank size */
+#define CONFIG_FLASH_ERASE_SIZE        0x800	/* erase bank size */
+/* This flash can only be written as 4-byte words (aligned properly, too). */
+#define CONFIG_FLASH_WRITE_SIZE        4	/* min write size (bytes) */
+/* But we have a 32-word buffer for writing multiple adjacent cells */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE  128	/* best write size (bytes) */
 
 /* Describe the flash layout */
-#define CONFIG_PROGRAM_MEMORY_BASE 0x40000
-#define CONFIG_FLASH_SIZE (512 * 1024)
+#define CONFIG_PROGRAM_MEMORY_BASE     0x40000
+#define CONFIG_FLASH_SIZE              (512 * 1024)
+#define CONFIG_RO_HEAD_ROOM	       1024	/* Room for ROM signature. */
 
 /* Compute the rest of the flash params from these */
 #include "config_std_internal_flash.h"