g: add ITE EC flash programming capability

This patch adds a callback function which triggers generation of the
ITE EC programming sequence by the H1.

It is going to be the board's code responsibility to configure ITE
SYNC mode at startup and then reset the H1. The expectation is that
when booting after reset the ITE SYNC sequence would be generated
before clock jitter is configured and locked.

ITE SYNC is a mode when soon after EC reset for duration of at least
20 ms the I2C master generates 200 KHz clock of the SDA line and 100
KHz clock on the SCL line, locked in phase, with 10% frequency
variation tolerance.

To be able to generate a stable 200 KHz clock jitter has to be
disabled, and the actual clock generation function needs to be written
in assembler, as this allows for the most accurate clock frequency
tuning.

The H1 GPIO controller allows to set multiple GPIO pins to requested
values in one 32 bit transaction. The C function maps I2C interface
directly to the GPIOs, prepares the address of the register to use to
control the GPIOs and the values to write to generate all four
combinations of the two signals: 00, 01, 10, 11.

Then it invokes the assembler function to actually generate the
clocks, and then re-enables the clock jitter.

BRANCH=cr50, cr50-mp
BUG=b:75976718
TEST=with the rest of the patches applied verified that it is possible
     to disable and re-enable clock jitter at run time.

Change-Id: Iac33c9bab68fc1ab919d960291176195a08f1791
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1263901
Reviewed-by: Mary Ruthven <mruthven@chromium.org>

1 files changed, 36 insertions, 0 deletions

diff --git a/chip/g/ite_sync.h b/chip/g/ite_sync.h
new file mode 100644
index 0000000000..c25dc57bc4
--- /dev/null
+++ b/chip/g/ite_sync.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CHIP_G_ITE_SYNC_H
+#define __CHIP_G_ITE_SYNC_H
+
+#include "util.h"
+
+/*
+ * Assembler function to generates ITE EC sync sequence, which requires two
+ * lines generating phase locked 200 KHz and 100 KHz clocks. This is achieved
+ * by directly togging two GPIOs.
+ *
+ * gpio_addr: address of the register to write to drive the GPIOs
+ * both_zero:
+ * one_zero:
+ * zero_one:
+ * both_one: values to write at gpio_addr to set the tow lines to these
+ *          stattes
+ * half_period_ticks: number of interations of the tight loop to last for half
+ *          the period of the higher frequency
+ * total_ticks_required: total ticks required to generate the sequence of the
+ *          necessary duration.
+ */
+void ite_sync(volatile uint16_t *gpio_addr, uint16_t both_zero,
+	      uint16_t one_zero, uint16_t zero_one, uint16_t both_one,
+	      uint32_t half_period_ticks, uint32_t total_ticks_required);
+
+
+/* Generate ITE SYNC sequence on the I2C interface controlling the EC. */
+void generate_ite_sync(void);
+
+#endif