cr50: sps: allow receive registration function set FIFO threshold

The default receive FIFO threshold of 8 (meaning that 9 bytes need to
be received before receive IRQ fires) is good for high volume
transfers, when the amount of transferred data greatly exceeds the
threshold.

But in case of TPM transactions, which start with a 4 byte header and
then stall while the device processes it, the default threshold
guarantees delays on every transaction, as the receiver does not start
processing the header until 5 idle bytes are transferred to bring the
total number to nine.

The suggested solution is to allow to specify the receive FIFO
interrupt request threshold at run time, by adding this value to the
receive function registration API.

BRANCH=none
BUG=chrome-os-partner:43025
TEST=verified that spstest still works fine.

Change-Id: I92517205a7d0d47893b702efa188eb524fb18a49
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289331
Reviewed-by: Bill Richardson <wfrichar@chromium.org>

1 files changed, 5 insertions, 1 deletions

diff --git a/chip/g/sps_tpm.c b/chip/g/sps_tpm.c
index 5ce79a661f..0dea0ce4ed 100644
--- a/chip/g/sps_tpm.c
+++ b/chip/g/sps_tpm.c
@@ -250,7 +250,11 @@ static void tpm_rx_handler(uint8_t *data, size_t data_size, int cs_disabled)
 
 static void sps_tpm_enable(void)
 {
-	sps_register_rx_handler(SPS_GENERIC_MODE, tpm_rx_handler);
+	/*
+	 * Let's make sure we get an interrupt as soon as the header is
+	 * received.
+	 */
+	sps_register_rx_handler(SPS_GENERIC_MODE, tpm_rx_handler, 3);
 	init_new_cycle();
 }