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| author | Vadim Bendebury <vbendeb@chromium.org> | 2015-11-02 20:36:07 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-11-05 11:10:32 -0800 |
| commit | a576355153ba9f41c630c64a9c511067151f06ad (patch) | |
| tree | d1c6c7438d66a47ff3cf9e2b3b7c59ca73023c21 /chip/g/uart.c | |
| parent | 032846bc3264a4d5ae82ad1efac9fc21ee64e88f (diff) | |
| download | chrome-ec-a576355153ba9f41c630c64a9c511067151f06ad.tar.gz | |
cr50: introduce RO image skeleton
The CR50 board will have to have a very different RO image, let's make
it possible to override the default list of objects compiled by the
top level makefile with a board/chip specific list compiled in the
appropriate build.mk file.
The CR50 RO will never run on its own for long time, it will always
load an RW and go straight to it, so there is no need in running under
the OS control, using sophisticated console channel controls, etc.
The gist of the functionality is verifying the RW image to run and
setting up the hardware to allow the picked image to execute, it will
be added in the following patches. This change just provides the
plumbing and shows the 'hello world' implementation for the customized
RO image.
A better solution could be the ability to create distinct sets of make
variables for RO and RW, a tracker item was created to look into this.
BRANCH=None
BUG=chrome-os-partner:43025, chromium:551151
TEST=built and started ec.RO.hex on cr50, observed the 'hello world'
message on the console.
Change-Id: Ie67ff28bec3a9788898e99483eedb0ef77de38cd
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/310410
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Diffstat (limited to 'chip/g/uart.c')
| -rw-r--r-- | chip/g/uart.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/chip/g/uart.c b/chip/g/uart.c index d48b6e3d9b..9af6990a1a 100644 --- a/chip/g/uart.c +++ b/chip/g/uart.c @@ -92,6 +92,7 @@ int uart_read_char(void) return GR_UART_RDATA(0); } +#ifndef SECTION_IS_RO void uart_disable_interrupt(void) { task_disable_irq(GC_IRQNUM_UART0_TXINT); @@ -126,6 +127,7 @@ void uart_ec_rx_interrupt(void) uart_process_input(); } DECLARE_IRQ(GC_IRQNUM_UART0_RXINT, uart_ec_rx_interrupt, 1); +#endif /* SECTION_IS_RO ^^^^^^ NOT defined. */ void uart_init(void) { @@ -149,8 +151,10 @@ void uart_init(void) /* Note: doesn't do anything unless turned on in NVIC */ GR_UART_ICTRL(0) = 0x02; +#ifndef SECTION_IS_RO /* Enable interrupts for UART0 only */ uart_enable_interrupt(); +#endif done_uart_init_yet = 1; } |