diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2017-10-31 18:54:34 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-11-08 03:12:23 -0800 |
| commit | e4579a29905dc08e4a6ed6156363b64bd03c5be3 (patch) | |
| tree | d90c4c690580107d3e2fe059e7c1a680f2db670f /chip/g | |
| parent | febb392391eee9d4f286dcf8a25b3d9d82a5be1e (diff) | |
| download | chrome-ec-e4579a29905dc08e4a6ed6156363b64bd03c5be3.tar.gz | |
g: sps: at initialization wait for the master to finish SPI cycle
TPM reset processing takes certain time, and conceivably the AP could
start SPI transactions before TPM reset is finished. If the SPS
interface comes up while the CS line is active, the H1 controller
considers this a start of the SPI cycle, even though it is not - the
AP has already transferred the header and is waiting for the flow
control.
Let's not complete SPS interface initialization while the CS line is
kept active.
BRANCH=cr50
BUG=b:68012381
TEST=verified that the AP firmware test passes
Change-Id: I53cd49c6139f3c29c4b6d234c7ee4d527c8282f6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/754504
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/g')
| -rw-r--r-- | chip/g/sps.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/chip/g/sps.c b/chip/g/sps.c index 6a78c5f7d5..d6d23e1d03 100644 --- a/chip/g/sps.c +++ b/chip/g/sps.c @@ -185,6 +185,20 @@ static void sps_configure(enum sps_mode mode, enum spi_clock_mode clk_mode, /* xfer 0xff when tx fifo is empty */ GREG32(SPS, DUMMY_WORD) = GC_SPS_DUMMY_WORD_DEFAULT; + if (!GREAD_FIELD(SPS, VAL, CSB)) { + /* + * Reset while the external controller is mid SPI + * transaction. + */ + ccprintf("%s: reset while CS active\n", __func__); + /* + * Wait for external controller to deassert CS before + * continuing. + */ + while (!GREAD_FIELD(SPS, VAL, CSB)) + ; + } + /* [5,4,3] [2,1,0] * RX{DIS, EN, RST} TX{DIS, EN, RST} */ |