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| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-09-04 19:09:33 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-09-16 14:49:31 -0700 |
| commit | d58e54730c03290296df5bb65cb84264e4b2facc (patch) | |
| tree | d736570c84a0e9737b8881ec68b073327a5c2ae5 /chip/host | |
| parent | 4b3c13ddfefd229dde49fb4cbf5a6bfc49f64973 (diff) | |
| download | chrome-ec-d58e54730c03290296df5bb65cb84264e4b2facc.tar.gz | |
cleanup: Rename geometry constants
Rename and add geometry constants to match spec doc -
https://goo.gl/fnzTvr.
CONFIG_FLASH_BASE becomes CONFIG_PROGRAM_MEMORY_BASE
CONFIG_FLASH_MAPPED becomes CONFIG_MAPPED_STORAGE
Add CONFIG_INTERNAL_STORAGE, CONFIG_EXTERNAL_STORAGE and
CONFIG_MAPPED_STORAGE_BASE where appropriate.
This CL leaves chip/npcx in a broken state -- it's fixed in a follow-up
CL.
BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images
Change-Id: Idb3c4ed9f7f6edd0a6d49ad11753eba713e67a80
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/297484
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/host')
| -rw-r--r-- | chip/host/config_chip.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/chip/host/config_chip.h b/chip/host/config_chip.h index 5df44a9315..eaaf46287f 100644 --- a/chip/host/config_chip.h +++ b/chip/host/config_chip.h @@ -12,13 +12,13 @@ #define CONFIG_FLASH_PHYSICAL_SIZE 0x00020000 extern char __host_flash[CONFIG_FLASH_PHYSICAL_SIZE]; -#define CONFIG_FLASH_BASE ((uintptr_t)__host_flash) -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0010 /* erase bank size */ -#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080 /* ideal write size */ -#define CONFIG_RAM_BASE 0x0 /* Not supported */ -#define CONFIG_RAM_SIZE 0x0 /* Not supported */ +#define CONFIG_PROGRAM_MEMORY_BASE ((uintptr_t)__host_flash) +#define CONFIG_FLASH_BANK_SIZE 0x1000 +#define CONFIG_FLASH_ERASE_SIZE 0x0010 /* erase bank size */ +#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080 /* ideal write size */ +#define CONFIG_RAM_BASE 0x0 /* Not supported */ +#define CONFIG_RAM_SIZE 0x0 /* Not supported */ #define CONFIG_FPU |