summaryrefslogtreecommitdiff
path: root/chip/ish/aontaskfw/ish_aontask.ld.in
diff options
context:
space:
mode:
authorHu, Hebo <hebo.hu@intel.com>2019-03-08 15:34:21 +0800
committerchrome-bot <chrome-bot@chromium.org>2019-04-08 02:51:29 -0700
commit6a184d5019f0b45fe692da09a14e9ce7c853d68c (patch)
tree541192356148342f09bacebb75bea95027e98e7d /chip/ish/aontaskfw/ish_aontask.ld.in
parentd0a350e6691a9d93138051e2aa00e0d6c26151b5 (diff)
downloadchrome-ec-6a184d5019f0b45fe692da09a14e9ce7c853d68c.tar.gz
ish/ish5: implement AON low power management framework
AON PM framework including: 1: AON task skeleton 2: task switching between main FW and AON task 3: 'idlestats' console command for D0ix statistic information 4: D0ix entrance in idle task BUG=b:122364080 BRANCH=none TEST=tested on arcada Change-Id: Iefa9e067892d5c42d9f0c795275fe88e5a36115b Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1510518 Commit-Ready: Rushikesh S Kadam <rushikesh.s.kadam@intel.com> Commit-Ready: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Diffstat (limited to 'chip/ish/aontaskfw/ish_aontask.ld.in')
-rw-r--r--chip/ish/aontaskfw/ish_aontask.ld.in68
1 files changed, 68 insertions, 0 deletions
diff --git a/chip/ish/aontaskfw/ish_aontask.ld.in b/chip/ish/aontaskfw/ish_aontask.ld.in
new file mode 100644
index 0000000000..a45bbdb6a9
--- /dev/null
+++ b/chip/ish/aontaskfw/ish_aontask.ld.in
@@ -0,0 +1,68 @@
+/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <config_chip.h>
+
+ENTRY(ish_aon_main);
+
+#define SRAM_START CONFIG_ISH_AON_SRAM_BASE_START
+#define SRAM_RW_LEN (CONFIG_ISH_AON_SRAM_SIZE - CONFIG_ISH_AON_SRAM_ROM_SIZE)
+
+/* reserved stack size */
+#define STACK_SIZE (256)
+
+/**
+ * resered 8 bytes for GDB showing correct stack
+ * information during source code level debuging
+ */
+#define RESERVED_GDB_SIZE (8)
+
+#define RAM_LEN (SRAM_RW_LEN - STACK_SIZE - RESERVED_GDB_SIZE)
+
+/**
+ * AON memory layout
+ * --------------+--------------+-------------------+-------------------+
+ * | RAM_LEN | STACK_SIZE | 8 Bytes for GDB | ROM(128 Bytes) |
+ * --------------+--------------+-------------------+-------------------+
+ */
+
+MEMORY
+{
+ /* leave STACK_SIZE bytes in the end of memory for stack */
+ RAM : ORIGIN = SRAM_START, LENGTH = RAM_LEN }
+
+SECTIONS
+{
+ /* AON parts visible to FW are linked to the beginning of the AON area */
+ .data.aon_share : AT(CONFIG_ISH_AON_SRAM_BASE_START)
+ {
+ KEEP(*(.data.aon_share))
+ } > RAM
+
+ .data :
+ {
+ *(.data)
+ *(.data*)
+ } > RAM
+
+ .text :
+ {
+ *(.text)
+ *(.text*)
+ } > RAM
+
+ .bss :
+ {
+ *(.bss)
+ *(.bss*)
+ } > RAM
+
+ .stack_tag :
+ {
+ KEEP(*(.stack_tag))
+ } > RAM
+
+
+}