diff options
| author | Hu, Hebo <hebo.hu@intel.com> | 2019-03-25 15:27:06 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-04-08 02:51:30 -0700 |
| commit | 6beb629714ce05108399cefc621b098fc58f03ce (patch) | |
| tree | 684dbf362a7f57f58e7d93939bdb555154d665f2 /chip/ish/aontaskfw | |
| parent | 014b6c86dfd1aa9ec9ffaba2647d4ca89baf1ef4 (diff) | |
| download | chrome-ec-6beb629714ce05108399cefc621b098fc58f03ce.tar.gz | |
ish/ish5: implement reset, reset_prep and D3 flow
1: reset and reset_prep implemented
2: D3 flow implemented
BUG=b:122364080
BRANCH=none
TEST=tested on arcada
Change-Id: Ie6bacd89e2363578d85157dfb1dd8b56e2828d05
Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1536486
Commit-Ready: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Tested-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Diffstat (limited to 'chip/ish/aontaskfw')
| -rw-r--r-- | chip/ish/aontaskfw/ish_aontask.c | 55 |
1 files changed, 42 insertions, 13 deletions
diff --git a/chip/ish/aontaskfw/ish_aontask.c b/chip/ish/aontaskfw/ish_aontask.c index e9992ae904..3426622357 100644 --- a/chip/ish/aontaskfw/ish_aontask.c +++ b/chip/ish/aontaskfw/ish_aontask.c @@ -76,7 +76,7 @@ #define AON_IDT_ENTRY_VEC_LAST ISH_PMU_WAKEUP_VEC #endif -static void handle_reset(void); +static void handle_reset(int pm_state); /* ISR for PMU wakeup interrupt */ static void pmu_wakeup_isr(void) @@ -108,7 +108,7 @@ static void reset_prep_isr(void) REG32(IOAPIC_EOI_REG) = ISH_RESET_PREP_VEC; REG32(LAPIC_EOI_REG) = 0x0; - handle_reset(); + handle_reset(ISH_PM_STATE_RESET_PREP); __builtin_unreachable(); } @@ -488,7 +488,7 @@ static void handle_d0i2(void) /* delay some cycles before halt */ delay(SRAM_RETENTION_CYCLES_DELAY); - ish_halt(); + ish_mia_halt(); /* wakeup from PMU interrupt */ /* set main SRAM intto normal mode */ @@ -516,7 +516,7 @@ static void handle_d0i3(void) /* power off main SRAM */ sram_power(0); - ish_halt(); + ish_mia_halt(); /* wakeup from PMU interrupt */ /* power on main SRAM */ @@ -527,22 +527,43 @@ static void handle_d0i3(void) if (ret != AON_SUCCESS) { /* we can't switch back to main FW now, reset ISH */ - handle_reset(); + handle_reset(ISH_PM_STATE_RESET); } } static void handle_d3(void) { - /* TODO store main FW 's context to IMR DDR from main sram */ - /* TODO power off main SRAM */ - - /* TODO handle D3 */ + /* handle D3 */ + handle_reset(ISH_PM_STATE_RESET); } -static void handle_reset(void) +static void handle_reset(int pm_state) { - /* TODO power off main SRAM */ - /* TODO handle reset */ + /* disable CSME CSR irq */ + REG32(IPC_PIMR) &= ~IPC_PIMR_CSME_CSR_BIT; + + /* power off main SRAM */ + sram_power(0); + + while (1) { + + /* check if host ish driver already set the DMA enable flag */ + if (REG32(IPC_ISH_RMP2) & DMA_ENABLED_MASK) { + + /* clear ISH2HOST doorbell register */ + REG32(IPC_ISH2HOST_DOORBELL) = 0; + + /* clear error register in MISC space */ + MISC_ISH_ECC_ERR_SRESP = 1; + + /* reset ISH minute-ia cpu core, will goto ISH ROM */ + ish_mia_reset(); + } + + ish_mia_halt(); + } + + __builtin_unreachable(); } static void handle_unknown_state(void) @@ -600,14 +621,22 @@ void ish_aon_main(void) case ISH_PM_STATE_D3: handle_d3(); break; + case ISH_PM_STATE_RESET: case ISH_PM_STATE_RESET_PREP: - handle_reset(); + handle_reset(aon_share.pm_state); break; default: handle_unknown_state(); break; } + /* check if D3 rising status */ + if (PMU_D3_STATUS & + (PMU_D3_BIT_RISING_EDGE_STATUS | PMU_D3_BIT_SET)) { + aon_share.pm_state = ISH_PM_STATE_D3; + handle_d3(); + } + /* restore main FW's IDT and switch back to main FW */ __asm__ volatile( "lidtl %0;\n" |