diff options
| author | Hu, Hebo <hebo.hu@intel.com> | 2019-05-08 17:12:59 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-05-12 19:27:51 -0700 |
| commit | b0b956cc0b17a04ffdff7d15292ecb33b4b8235b (patch) | |
| tree | 49d7c8fcac8aa0d6fc457428314f290388c70053 /chip/ish/aontaskfw | |
| parent | 1fd8e3b0c5609612cf3339edab73bd7b7bb93f54 (diff) | |
| download | chrome-ec-b0b956cc0b17a04ffdff7d15292ecb33b4b8235b.tar.gz | |
ish/ish5: fixed both-edge triggered gpio configuration blocking D0ix issue
ISH PMU does not support both-edge interrupt triggered gpio configuration.
If both edges are configured, then the ISH can't stay in low power mode
because it will exit immediately.
As a W/A, we scan all gpio pins which have been configured as both-edge
triggered, and then temporarily set each gpio pin to the single edge
trigger that is opposite of its value, then restore the both-edge
trigger configuration immediately after exiting low power mode.
BUG=b:132001235
BRANCH=none
TEST= tested on arcada platform, console should freeze after entered low
power mode
Change-Id: I83a43d9fbee6cfd1a6820bdb44c1446f109ffb32
Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1600310
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Diffstat (limited to 'chip/ish/aontaskfw')
| -rw-r--r-- | chip/ish/aontaskfw/ish_aontask.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/chip/ish/aontaskfw/ish_aontask.c b/chip/ish/aontaskfw/ish_aontask.c index 95b6d9ce5d..7c0809b4a2 100644 --- a/chip/ish/aontaskfw/ish_aontask.c +++ b/chip/ish/aontaskfw/ish_aontask.c @@ -546,6 +546,11 @@ static void handle_reset(int pm_state) /* disable watch dog */ WDT_CONTROL &= ~WDT_CONTROL_ENABLE_BIT; + /* disable all gpio interrupts */ + ISH_GPIO_GRER = 0; + ISH_GPIO_GFER = 0; + ISH_GPIO_GIMR = 0; + /* disable CSME CSR irq */ IPC_PIMR &= ~IPC_PIMR_CSME_CSR_BIT; |