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| author | Leifu Zhao <leifu.zhao@intel.com> | 2019-10-08 13:28:20 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-11-09 00:24:06 +0000 |
| commit | d8db28afe8e93a358ab8e9b656cfcb4f4681a222 (patch) | |
| tree | cbe6d4829f3f59ea3b3ae9558e43ed0ae764c3f2 /chip/ish/config_chip.h | |
| parent | b70a82f452c0f1b62bd0c7d44981b72a6924852c (diff) | |
| download | chrome-ec-d8db28afe8e93a358ab8e9b656cfcb4f4681a222.tar.gz | |
ish: chip enablement of ish5.4 on tgl rvp platform
Chip level enablement of ish5.4 on tgl rvp platform.
BUG=b:141519691
BRANCH=none
TEST=tested on tgl rvp
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
Change-Id: I3f6249e1816d81deec0420a12b093918ee7fbddc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1846788
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Commit-Queue: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Diffstat (limited to 'chip/ish/config_chip.h')
| -rw-r--r-- | chip/ish/config_chip.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/chip/ish/config_chip.h b/chip/ish/config_chip.h index 148341db47..b4dea95767 100644 --- a/chip/ish/config_chip.h +++ b/chip/ish/config_chip.h @@ -35,7 +35,11 @@ /* Memory Layout */ /*****************************************************************************/ +#ifdef CHIP_VARIANT_ISH5P4 +#define CONFIG_RAM_BASE 0xFF200000 +#else #define CONFIG_RAM_BASE 0xFF000000 +#endif #define CONFIG_RAM_SIZE 0x000A0000 #define CONFIG_RAM_BANK_SIZE 0x00008000 @@ -115,4 +119,14 @@ #define GPIO_PIN(index) 0, (1 << (index)) #define GPIO_PIN_MASK(m) .port = 0, .mask = (m) +#ifdef CHIP_VARIANT_ISH5P4 +/* Use combined ISR for ipc communication between host and ISH */ +#define CONFIG_ISH_HOST2ISH_COMBINED_ISR +/* Use Synopsys Designware uart */ +#define CONFIG_ISH_DW_UART +#else +/* Need to clear ISH fabric error */ +#define CONFIG_ISH_CLEAR_FABRIC_ERRORS +#endif + #endif /* __CROS_EC_CONFIG_CHIP_H */ |